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P8254 Datasheet(PDF) 11 Page - Intersil Corporation |
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P8254 Datasheet(HTML) 11 Page - Intersil Corporation |
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11 / 17 page  4-11 FIGURE 13. MODE 4 Mode 5: Hardware Triggered Strobe (Retriggerable) OUT will initially be high. Counting is triggered by a rising edge of GATE. When the initial count has expired, OUT will go low for one CLK pulse and then go high again. After writing the Control Word and initial count, the counter will not be loaded until the CLK pulse after a trigger. This CLK pulse does not decrement the count, so for an initial count of N, OUT does not strobe low until N + 1 CLK pulses after trigger. A trigger results in the Counter being loaded with the initial count on the next CLK pulse. The counting sequence is trig- gerable. OUT will not strobe low for N + 1 CLK pulses after any trigger GATE has no effect on OUT. If a new count is written during counting, the current count- ing sequence will not be affected. If a trigger occurs after the new count is written but before the current count expires, the Counter will be loaded with new count on the next CLK pulse and counting will continue from there. FIGURE 14. MODE 5 Operation Common to All Modes Programming When a Control Word is written to a Counter, all Control Logic, is immediately reset and OUT goes to a known initial state; no CLK pulses are required for this. Gate The GATE input is always sampled on the rising edge of CLK. In Modes 0, 2, 3 and 4 the GATE input is level sensi- tive, and logic level is sampled on the rising edge of CLK. In modes 1, 2, 3 and 5 the GATE input is rising-edge sensitive. In these Modes, a rising edge of Gate (trigger) sets an edge- sensitive flip-flop in the Counter. This flip-flop is then sam- pled on the next rising edge of CLK. The flip-flop is reset immediately after it is sampled. In this way, a trigger will be detected no matter when it occurs - a high logic level does not have to be maintained until the next rising edge of CLK. Note that in Modes 2 and 3, the GATE input is both edge- and level-sensitive. NNN N 0 2 0 1 0 0 FF FF FF FE FF FD 0 3 WR CLK GATE OUT CW = 18 LSB = 3 WR CLK GATE OUT WR CLK GATE OUT CW = 18 LSB = 3 CW = 18 LSB = 3 NN N 0 3 0 2 0 1 0 2 0 1 0 0 FF FF NN N N 0 3 0 3 0 2 0 1 0 0 FF FF 0 3 LSB = 2 N NN N N 0 3 0 2 0 1 0 0 FF FF 0 3 WR CLK GATE OUT CW = 1A LSB = 3 NN N N 0 3 0 2 0 3 0 2 0 1 NN N N 0 3 0 2 0 1 0 0 FF FF FF FE WR CLK GATE OUT CW = 1A LSB = 3 WR CLK GATE OUT CW = 1A LSB = 3 N NN 0 0 FF FF LSB = 5 N 0 5 0 4 82C54 |
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Similar Description - P8254 |
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