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ACTS112K Datasheet(PDF) 1 Page - Intersil Corporation |
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ACTS112K Datasheet(HTML) 1 Page - Intersil Corporation |
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1 / 3 page  1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 ACTS112MS Radiation Hardened Dual J-K Flip-Flop Pinouts 16 PIN CERAMIC DUAL-IN-LINE MIL-STD-1835, DESIGNATOR CDIP2-T16, LEAD FINISH C TOP VIEW 16 PIN CERAMIC FLATPACK MIL-STD-1835, DESIGNATOR CDFP4-F16, LEAD FINISH C TOP VIEW 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 CP1 K1 J1 S1 Q1 Q1 GND Q2 VCC R2 CP2 K2 J2 S2 Q2 R1 CP1 K1 J1 S1 Q1 Q1 Q2 GND 2 3 4 5 6 7 8 116 15 14 13 12 11 10 9 VCC R1 R2 CP2 K2 J2 S2 Q2 Features • Devices QML Qualified in Accordance with MIL-PRF-38535 • Detailed Electrical and Screening Requirements are Contained in SMD# 5962-96714 and Intersil’s QM Plan • 1.25 Micron Radiation Hardened SOS CMOS • Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si) • Single Event Upset (SEU) Immunity: <1 x 10-10 Errors/Bit/Day (Typ) • SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100 MEV-cm2/mg • Dose Rate Upset . . . . . . . . . . . . . . . . >1011 RAD (Si)/s, 20ns Pulse • Dose Rate Survivability . . . . . . . . . . . >1012 RAD (Si)/s, 20ns Pulse • Latch-Up Free Under Any Conditions • Military Temperature Range . . . . . . . . . . . . . . . . . . -55oC to +125oC • Significant Power Reduction Compared to ALSTTL Logic • DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V • Input Logic Levels - VIL = 0.8V Max - VIH = VCC/2 Min • Input Current ≤ 1µA at VOL, VOH • Fast Propagation Delay . . . . . . . . . . . . . . . . 26ns (Max), 16ns (Typ) Description The Intersil ACTS112MS is a Radiation Hardened Dual J-K Flip-Flop with Set and Reset. The output change states on the negative transition of the clock (CP1N or CP2N). The ACTS112MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family. The ACTS112MS is supplied in a 16 lead Ceramic Flatpack (K suffix) or a Ceramic Dual-In-Line Package (D suffix). January 1996 Ordering Information PART NUMBER TEMPERATURE RANGE SCREENING LEVEL PACKAGE 5962F9671401VEC -55oC to +125oC MIL-PRF-38535 Class V 16 Lead SBDIP 5962F9671401VXC -55oC to +125oC MIL-PRF-38535 Class V 16 Lead Ceramic Flatpack ACTS112D/Sample 25oC Sample 16 Lead SBDIP ACTS112K/Sample 25oC Sample 16 Lead Ceramic Flatpack ACTS112HMSR 25oC Die Die Spec Number 518825 File Number 3570.1 |
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