AD7366-5/AD7367-5

Rev. B | Page 9 of 28

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

2

3

ADDR

4

DGND

24

23

BUSY

22

CNVST

21

RANGE1

6

SCLK

20

CS

19

REFSEL

18

8

AGND

17

9

16

10

15

11

14

12

13

AD7366-5/

AD7367-5

TOP VIEW

(Not to Scale)

Figure 2. Pin Configuration

Table 6. Pin Function Descriptions

Pin No.

Mnemonic

Description

1, 23

Serial Data Outputs. The data output is supplied to each pin as a serial data stream. The bits are clocked out on

the falling edge of the SCLK input and 12 SCLK cycles are required to access the data from the AD7366-5 while

14 SCLK cycle are required for the AD7367-5. The data simultaneously appears on both pins from the simultaneous

conversions of both ADCs. The data stream consists of the 12 bits of conversion data for the AD7366-5 and 14 bits

for the AD7367-5 and is provided MSB first. If CS is held low for a further 12 SCLK cycles for the AD7366-5 or 14 SCLK

section for more information.

Serial Interface

2

Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface operates.

This pin should be decoupled to DGND. The voltage range on this pin is 2.7 V to 5.25 V and may be different than

3

voltage difference between them never exceeds 0.3 V, even on a transient basis. This supply should be decoupled

4, 5

RANGE1,

RANGE0

Analog Input Range Selection, Logic Inputs. The polarity on these pins determines the input range of the analog

input channels. See the Analog Inputs section and Table 8 for details.

6

ADDR

Multiplexer Select, Logic Input. This input is used to select the pair of channels to be simultaneously converted,

either Channel 1 of both ADC A and ADC B, or Channel 2 of both ADC A and ADC B. The logic state on this pin is

latched on the rising edge of BUSY to set up the multiplexer for the next conversion.

7, 17

AGND

Analog Ground. Ground reference point for all analog circuitry on the AD7366-5/AD7367-5. All analog input

signals and any external reference signal should be referred to this AGND voltage. Both AGND pins should

connect to the AGND plane of a system. The AGND and DGND voltages ideally should be at the same potential

and must not be more than 0.3 V apart, even on a transient basis.

8

shorted together to ensure that the voltage difference between them never exceeds 0.3 V even on a transient

9, 16

Decoupling Capacitor Pins. Decoupling capacitors are connected to these pins to decouple the reference buffer

for each respective ADC. For best performance, it is recommended to use a 680 nF decoupling capacitor on these

pins. Provided the output is buffered, the on-chip reference can be taken from these pins and applied externally

to the rest of a system.

10

Negative Power Supply Voltage. This is the negative supply voltage for the high voltage analog input structure

of the AD7366-5/AD7367-5. The supply must be less than or equal to −5 V (see Table 7 for further details).

11, 12

Analog Inputs of ADC A. These are both single-ended analog inputs. The analog input range on these channels is

determined by the RANGE0 and RANGE1 pins.

13, 14

Analog Inputs of ADC B. These are both single-ended analog inputs. The analog input range on these channels is

determined by the RANGE0 and RANGE1 pins.

15

Positive Power Supply Voltage. This is the positive supply voltage for the high voltage analog input structure

of the AD7366-5/AD7367-5. The supply must be greater than or equal to 5 V (see Table 7 for further details).