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ADC0804 Datasheet(PDF) 9 Page - Intersil Corporation |
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ADC0804 Datasheet(HTML) 9 Page - Intersil Corporation |
9 / 16 page 6-13 The device may be operated in the free-running mode by con- necting INTR to the WR input with CS = 0. To ensure start-up under all possible conditions, an external WR pulse is required during the first power-up cycle. A conversion-in-pro- cess can be interrupted by issuing a second start command. Digital Operation The converter is started by having CS and WR simultaneously low. This sets the start flip-flop (F/F) and the resulting “1” level resets the 8-bit shift register, resets the Interrupt (INTR) F/F and inputs a “1” to the D flip-flop, DFF1, which is at the input end of the 8-bit shift register. Internal clock signals then trans- fer this “1” to the Q output of DFF1. The AND gate, G1, com- bines this “1” output with a clock signal to provide a reset signal to the start F/F. If the set signal is no longer present (either WR or CS is a “1”), the start F/F is reset and the 8-bit shift register then can have the “1” clocked in, which starts the conversion process. If the set signal were to still be present, this reset pulse would have no effect (both outputs of the start F/F would be at a “1” level) and the 8-bit shift register would continue to be held in the reset mode. This allows for asyn- chronous or wide CS and WR signals. After the “1” is clocked through the 8-bit shift register (which completes the SAR operation) it appears as the input to DFF2. As soon as this “1” is output from the shift register, the AND gate, G2, causes the new digital word to transfer to the Three-State output latches. When DFF2 is subsequently clocked, the Q output makes a high-to-low transition which causes the INTR F/F to set. An inverting buffer then supplies the INTR output signal. When data is to be read, the combination of both CS and RD being low will cause the INTR F/F to be reset and the three- state output latches will be enabled to provide the 8-bit digital outputs. Digital Control Inputs The digital control inputs (CS, RD, and WR) meet standard TTL logic voltage levels. These signals are essentially equiva- lent to the standard A/D Start and Output Enable control sig- nals, and are active low to allow an easy interface to microprocessor control busses. For non-microprocessor based applications, the CS input (pin 1) can be grounded and the standard A/D Start function obtained by an active low pulse at the WR input (pin 3). The Output Enable function is achieved by an active low pulse at the RD input (pin 2). Analog Operation The analog comparisons are performed by a capacitive charge summing circuit. Three capacitors (with precise ratioed values) share a common node with the input to an auto-zeroed comparator. The input capacitor is switched between VlN(+) and VlN(-), while two ratioed reference capaci- tors are switched between taps on the reference voltage divider string. The net charge corresponds to the weighted dif- ference between the input and the current total value set by the successive approximation register. A correction is made to offset the comparison by 1/2 LSB (see Figure 11A). Analog Differential Voltage Inputs and Common-Mode Rejection This A/D gains considerable applications flexibility from the ana- log differential voltage input. The VlN(-) input (pin 7) can be used to automatically subtract a fixed voltage value from the input reading (tare correction). This is also useful in 4mA - 20mA cur- rent loop conversion. In addition, common-mode noise can be reduced by use of the differential input. The time interval between sampling VIN(+) and VlN(-) is 4 1/ 2 clock periods. The maximum error voltage due to this slight time difference between the input voltage samples is given by: where: ∆VE is the error voltage due to sampling delay, VPEAK is the peak value of the common-mode voltage, fCM is the common-mode frequency. For example, with a 60Hz common-mode frequency, fCM, and a 640kHz A/D clock, fCLK, keeping this error to 1/ 4 LSB (~5mV) would allow a common-mode voltage, VPEAK, given by: , or . The allowed range of analog input voltage usually places more severe restrictions on input common-mode voltage levels than this. An analog input voltage with a reduced span and a relatively large zero offset can be easily handled by making use of the differential input (see Reference Voltage Span Adjust). Analog Input Current The internal switching action causes displacement currents to flow at the analog inputs. The voltage on the on-chip capaci- tance to ground is switched through the analog differential input voltage, resulting in proportional currents entering the VIN(+) input and leaving the VIN(-) input. These current tran- sients occur at the leading edge of the internal clocks. They rapidly decay and do not inherently cause errors as the on- chip comparator is strobed at the end of the clock perIod. Input Bypass Capacitors Bypass capacitors at the inputs will average these charges and cause a DC current to flow through the output resistances of the analog signal sources. This charge pumping action is worse for continuous conversions with the VIN(+) input voltage at full scale. For a 640kHz clock frequency with the VIN(+) input at 5V, this DC current is at a maximum of approximately 5 µA. Therefore, bypass capacitors should not be used at the analog inputs or the VREF/2 pin for high resistance sources (>1k Ω). If input bypass capacitors are necessary for noise filtering and high source resistance is desirable to mini- mize capacitor size, the effects of the voltage drop across this input resistance, due to the average value of the input current, can be compensated by a full scale adjustment while the given source resistor and input bypass capacitor are both in place. This is possible because the average value of the input current is a precise linear function of the differential input voltage at a constant conversion rate. V E MAX () ∆ V PEAK () 2πf CM () 4.5 f CLK ------------ = V PEAK ∆V E MAX () f CLK () 2 πf CM () 4.5 () -------------------------------------------------- = V PEAK 510 3 – × () 640 10 3 × () 6.28 () 60 () 4.5 () ---------------------------------------------------------- 1.9V ≅ = ADC0802, ADC0803, ADC0804 |
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