Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.NET

X  

AD7711 Datasheet(PDF) 8 Page - Analog Devices

Part # AD7711
Description  LC MOS Signal Conditioning ADC
Download  28 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD7711 Datasheet(HTML) 8 Page - Analog Devices

Back Button AD7711_15 Datasheet HTML 4Page - Analog Devices AD7711_15 Datasheet HTML 5Page - Analog Devices AD7711_15 Datasheet HTML 6Page - Analog Devices AD7711_15 Datasheet HTML 7Page - Analog Devices AD7711_15 Datasheet HTML 8Page - Analog Devices AD7711_15 Datasheet HTML 9Page - Analog Devices AD7711_15 Datasheet HTML 10Page - Analog Devices AD7711_15 Datasheet HTML 11Page - Analog Devices AD7711_15 Datasheet HTML 12Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 8 / 28 page
background image
REV. G
–8–
AD7711
Pin
Mnemonic
Function
20
RFS
Receive Frame Synchronization. Active low logic input used to access serial data from the device. In the
self-clocking mode, the SCLK and SDATA lines both become active after
RFS goes low. In the external
clocking mode, the SDATA line becomes active after
RFS goes low.
21
DRDY
Logic Output. A falling edge indicates that a new output word is available for transmission. The
DRDY pin
will return high upon completion of transmission of a full output word.
DRDY is also used to indicate
when the AD7711 has completed its on-chip calibration sequence.
22
SDATA
Serial Data. Input/output with serial data being written to either the control register or the calibration
registers and serial data being accessed from the control register, calibration registers, or the data register.
During an output data read operation, serial data becomes active after
RFS goes low (provided DRDY is
low). During a write operation, valid serial data is expected on the rising edges of SCLK when
TFS is low.
The output data coding is natural binary for unipolar inputs and offset binary for bipolar inputs.
23
DVDD
Digital Supply Voltage, 5 V. DVDD should not exceed AVDD by more than 0.3 V in normal operation.
24
DGND
Ground Reference Point for Digital Circuitry.
TERMINOLOGY
Intergral Nonlinearity
This is the maximum deviation of any code from a straight line
passing through the endpoints of the transfer function. The end-
points of the transfer function are zero-scale (not to be confused
with bipolar zero), a point 0.5 LSB below the first code transi-
tion (000 . . . 000 to 000 . . . 001) and full scale, a point 0.5 LSB
above the last code transition (111 . . . 110 to 111 . . . 111). The
error is expressed as a percentage of full scale.
Positive Full-Scale Error
Positive full-scale error is the deviation of the last code transi-
tion (111 . . . 110 to 111 . . . 111) from the ideal input full-scale
voltage. For AIN1(+), the ideal full-scale input voltage is
(AIN1(–) + VREF/GAIN – 3/2 LSBs); for AIN2, the ideal full-
scale input voltage is VREF/GAIN – 3/2 LSBs. It applies to both
unipolar and bipolar analog input ranges.
Unipolar Offset Error
Unipolar offset error is the deviation of the first code transition
from the ideal voltage. For AIN1(+), the ideal input voltage is
(AIN1(–) + 0.5 LSB); for AIN2, the ideal input is 0.5 LSB
when operating in the unipolar mode.
Bipolar Zero Error
This is the deviation of the midscale transition (0111 . . . 111
to 1000 . . . 000) from the ideal input voltage. For AIN1(+), the
ideal input voltage is (AIN1(–) – 0.5 LSB); for AIN2, the ideal
input is – 0.5 LSB when operating in the bipolar mode.
Bipolar Negative Full-Scale Error
This is the deviation of the first code transition from the ideal
input voltage. For (AIN1(+), the ideal input voltage is (AIN1(–)
– VREF/GAIN + 0.5 LSB); for AIN2 the ideal input is – VREF/GAIN
+ 0.5 LSB when operating in the bipolar mode.
Positive Full-Scale Overrange
Positive full-scale overrange is the amount of overhead avail-
able to handle input voltages on the AIN1(+) input greater
than AIN1(–) + VREF/GAIN or on the AIN2 input greater
than + VREF/GAIN (for example, noise peaks or excess
voltages due to system gain errors in system calibration rou-
tines) without introducing errors due to overloading the analog
modulator or to overflowing the digital filter.
Negative Full-Scale Overrange
This is the amount of overhead available to handle voltages on
AIN1(+) below AIN1(–) – VREF/GAIN or on AIN2 below
–VREF/GAIN without overloading the analog modulator or over-
flowing the digital filter. Note that the analog input will accept
negative voltage peaks on AIN1(+) even in the unipolar mode
provided that AIN1(+) is greater than AIN1(–) and greater than
VSS – 30 mV.
Offset Calibration Range
In the system calibration modes, the AD7711 calibrates its
offset with respect to the analog input. The offset calibration
range specification defines the range of voltages that the AD7711
can accept and still calibrate offset accurately.
Full-Scale Calibration Range
This is the range of voltages that the AD7711 can accept in the
system calibration mode and still calibrate full-scale correctly.
Input Span
In system calibration schemes, two voltages applied in sequence
to the AD7711’s analog input define the analog input range.
The input span specification defines the minimum and maxi-
mum input voltages from zero- to full-scale that the AD7711
can accept and still calibrate gain accurately.


Similar Part No. - AD7711_15

ManufacturerPart #DatasheetDescription
logo
Analog Devices
AD7711 AD-AD7711_17 Datasheet
354Kb / 29P
   Signal Conditioning ADC
More results

Similar Description - AD7711_15

ManufacturerPart #DatasheetDescription
logo
Analog Devices
AD7711A AD-AD7711A_15 Datasheet
329Kb / 28P
   LC MOS Signal Conditioning ADC
REV. D
AD7712 AD-AD7712_15 Datasheet
258Kb / 28P
   Signal Conditioning ADC
REV. F
AD7711 AD-AD7711_17 Datasheet
354Kb / 29P
   Signal Conditioning ADC
AD7714 AD-AD7714_17 Datasheet
349Kb / 41P
   Signal Conditioning ADC
AD7710 AD-AD7710 Datasheet
220Kb / 28P
   Signal Conditioning ADC
REV. F
AD7710ANZ AD-AD7710ANZ Datasheet
265Kb / 32P
   Signal Conditioning ADC
REV. G
AD7712 AD-AD7712_17 Datasheet
304Kb / 29P
   Signal Conditioning ADC
AD7710 AD-AD7710_17 Datasheet
319Kb / 33P
   Signal Conditioning ADC
AD7710AR-REEL7 AD-AD7710AR-REEL7 Datasheet
265Kb / 32P
   Signal Conditioning ADC
REV. G
AD7714 AD-AD7714_15 Datasheet
298Kb / 40P
   Signal Conditioning ADC
REV. C
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.NET
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com