7-1440

CD40208BMS

FIGURE 11. POWER-DISSIPATION TEST CIRCUIT AND WAVEFORMS

FIGURE 12. OUTPUT-ENABLE-DELAY-TIMES TEST CIRCUIT AND WAVEFORMS

1

2

3

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5

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10

11

12

16

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21

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13

PULSE GEN. 1

PULSE GEN. 2

(fI)

P.G. 1

P.G. 2

P.G. 3

REPETITIVE WAVEFORMS

ID

500

µF

VDD

0.1

µF

CL

CL

CL

PULSE GEN. 3

CL

CL

CL

CL

CL

Qn A, B

CHAR

TEST VOLTAGE

AT D

AT Q

tPHZ

VDD

VSS

tPZH

VDD

VSS

tPLZ

VSS

VDD

tPZL

VSS

VDD

1

2

3

4

5

6

7

8

9

10

11

12

16

17

18

19

20

21

22

23

24

15

14

13

PULSE GEN. 1

D

PULSE GEN. 2

TO ANY

OUTPUT

1k

Ω

50pF

Q

VDD

10%

90%

10%

90%

50%

50%

tPLZ

tPZL

Q

OUTPUTS

tPHZ

tPZH

VSS

VOH

VOL

VSS

VDD

VDD

ENABLE

CL

P.G. 1

P.G. 2

ENABLE

INPUT