AD7869

–6–

CONVERTER DETAILS

The AD7869 is a complete 14-bit I/O port; the only external

components required for normal operation are pull-up resistors

for the ADC data outputs, and power supply decoupling capaci-

tors. The AD7869 is comprised of a 14-bit successive approxi-

mation ADC with a track/hold amplifier, a 14-bit DAC with a

buffered output and two 3 V buried Zener references, a clock os-

cillator and control logic.

ADC CLOCK

The AD7869 has an internal clock oscillator that can be used for

the ADC conversion procedure. The oscillator is enabled by ty-

factory to give a maximum conversion time of 10

µs. The mark/

space ratio can vary from 40/60 to 60/40. Alternatively, an exter-

nal TTL compatible clock may be applied to this input. The al-

lowable mark/space ratio of an external clock is 40/60 to 60/40.

RCLK is a clock output, used for the serial interface. This out-

put is derived directly from the ADC clock source and can be

switched off at the end of conversion with the CONTROL

input.

ADC CONVERSION TIMING

The conversion time for both external clock and continuous in-

ternal clock can vary from 19 to 20 rising clock edges, depending

on the conversion start to ADC clock synchronization. If a con-

version is initiated within 30 ns prior to a rising edge of the ADC

clock, the conversion time will consist of 20 rising clock edges,

i.e., 9.5

µs conversion time. For noncontinuous internal clock,

the conversion time always consists of 19 rising clock edges.

ADC TRACK-AND-HOLD AMPLIFIER

The track-and-hold amplifier on the analog input of the AD7869

allows the ADC to accurately convert an input sine wave of 6 V

peak–peak amplitude to 14-bit accuracy. The input impedance is

typically 9 k

Ω; an equivalent circuit is shown in Figure 1. The

input bandwidth of the track/hold amplifier is much greater

than the Nyquist rate of the ADC even when the ADC is oper-

ated at its maximum throughput rate. The 0.1 dB cutoff fre-

quency occurs typically at 500 kHz. The track/hold amplifier

acquires an input signal to 14-bit accuracy in less than 2

µs. The

overall throughput rate is equal to the conversion time plus the

track/hold amplifier acquisition time. For a 2.0 MHz input clock,

the throughput time is 12

µs max.

AD7869*

4.5k

Ω

4.5k

Ω

*ADDITIONAL PINS OMITTED FOR CLARITY

TO INTERNAL

COMPARATOR

TRACK/HOLD

AMPLIFIER

TO INTERNAL

3V REFERENCE

Figure 1. ADC Analog Input

The operation of the track/hold amplifier is essentially transpar-

ent to the user. The track/hold amplifier goes from its track

mode to its hold mode at the start of conversion on the rising

edge of

CONVST.

INTERNAL REFERENCES

The AD7869 has two on-chip temperature compensated buried

Zener references that are factory trimmed to 3 V

±10 mV. One

reference provides the appropriate biasing for the ADC, while

the other is available as a reference for the DAC. Both reference

outputs are available (labelled RO DAC and RO ADC) and are

capable of providing up to 500

µA to an external load.

The DAC input reference (RI DAC) can be sourced externally

or connected to any of the two on-chip references. Applications

requiring good full-scale error matching between the DAC and

the ADC should use the ADC reference as shown in Figure 4.

The maximum recommended capacitance on either of the refer-

ence output pins for normal operation is 50 pF. If either of the

reference outputs is required to drive a capacitive load greater

than 50 pF, then a 200

Ω resistor must be placed in series with

the capacitive load. The addition of decoupling capacitors,

10

µF in parallel with 0.1 µF as shown in Figure 2, improves

noise performance. The improvement in noise performance can

be seen from the graph in Figure 3. Note: this applies for the

DAC output only; reference decoupling components do not af-

fect ADC performance. Consequently, a typical application will

have just the DAC reference decoupled with the other one open

circuited.

RI DAC

200

Ω

RO DAC

or

RO ADC*

EXT LOAD

GREATER THAN 50pF

*RO DAC/RO ADC CAN BE LEFT

OPEN CIRCUIT IF NOT USED

10

µF

0.1

µF

Figure 2. Reference Decoupling Components

DAC OUTPUT AMPLIFIER

The output from the voltage mode DAC is buffered by a non-

inverting amplifier. The buffer amplifier is capable of developing

±3 V across 2 kΩ and 100 pF load to ground and can produce

6 V peak-to-peak sine wave signals to a frequency of 20 kHz.

The output is updated on the falling edge of the LDAC input.

The output voltage settling time, to within 1/2 LSB of its final

value, is typically less than 3.5

µs.

The small signal (200 mV p–p) bandwidth of the output buffer

amplifier is typically 1 MHz. The output noise from the ampli-

fier is low with a figure of 30 nV/

√Hz at a frequency of 1 kHz.

The broadband noise from the amplifier exhibits a typical peak-

to-peak figure of 150

µV for a 1 MHz output bandwidth. Figure

3 shows a typical plot of noise spectral density versus frequency

for the output buffer amplifier and for either of the on-chip

references.

REV. B