CD4063 datasheet(6/8 Pages) INTERSIL

Part #	CD4063

Description	CMOS 4-Bit Magnitude Comparator

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Manufacturer	INTERSIL [Intersil Corporation]

Direct Link	http://www.intersil.com/cda/home

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7-963

CD4063BMS

Logic Diagram

FIGURE 2. LOGIC DIAGRAM

TRUTH TABLE

INPUTS

OUTPUTS

COMPARING

CASCADING

A3, B3

A2, B2

A1, B1

A0, B0

A <B

A = B

A > B

A < B

A = B

A > B

A3 > B3

A3 = B3

X

A2 > B2

A2 = B2

X

A1 > B1

A1 = B1

X

A0 > B0

X

0

1

A3 = B3

A2 = B2

A1 = B1

A0 = B0

0

1

0

1

0

1

0

1

0

1

0

1

0

A3 = B3

A3 < B3

A2 = B2

A2 < B2

X

A1 = B1

A1 < B1

X

A0 < B0

X

1

0

X = Don’t Care

Logic 1 = High Level

Logic 0 = Low Level

10

*

A0

12

*

A1

13

*

A2

15

*

A3

9

*

B0

11

*

B1

14

*

B2

1

*

B3

2

*

4

*

3

*

A3

B3

A3

B3

A2

B2

A2

B2

A1

B1

A1

B1

A0

B0

A0

B0

(A < B) i - I

ALL INPUTS PROTECTED

BY THE CMOS

PROTECTION NETWORK

*

VDD

VSS

INPUT

TERMINAL

A3

B3

A3

B3

A2

B2

A2

B2

A1

B1

A1

B1

A0

B0

A0

B0

(A > B) i - I

A < B

A > B

(A < B) OUT

7

(A = B) OUT

6

(A > B) OUT

5

A0

A1

A2

A3

B0

B1

B2

B3

(A < B) i - I

(A > B) i - I

(A < B) IN

(A > B) IN

(A = B) IN

COMPARING

INPUTS

CASCADING

INPUTS

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