7-1242

CD4536BMS

FIGURE 1.

(Continued)

R

φ

Q

Q

φ

FF24

R

φ

Q

Q

φ

R

φ

Q

Q

φ

R

CL

Q

Q

D

R

CL

Q

Q

CLDIS

FF9

FF10

FF11

FF16

p

n

p

n

R

φ

Q

Q

φ

R

Q

Q

FF17

FF18

φ

φ

1 OF 16 DECODER (TRANSMISSION-GATE TREE LOGIC)

*

D

12

*

C

11

*

B

10

*

A

9

N

P

VSS

*

15

MONO IN

DECODE

OUT

13

G

F

E

D

C

B

A

P

VSS

φ

P

N

N

φ

P

P

N

N

φ

φ

N

R

pn

p

n

φ

φ

P

P

N

N

R

φ

φ

N

VDD

Q

Q

R

Q

φ

φ

Q

DETAIL FOR

FF3-8, 11-16, 17-24

p

n

e

Q

CLEN (CLDIS FOR FF9 AND FF25)

p

n

f

Q

f

p

n

a

D

φ

φ

p

n

b

φ

φ

a

R

φ

φ

p

n

d

φ

φ

p

n

c

d

b

c

R

Q

Q

R

S

DETAIL FOR

FF1, FF2, FF10, FF9, FF25

R

CLEN

CL

Q

e

φ

φ

CL

FF1

R

D

CL

Q

FF2, 10

R

CLDIS

CL

Q

FF9

R

CLDIS

CL

Q

FF25

S

Q

Q

Q

FF1: AS SHOWN EXCEPT Q NOT BROUGHT OUT

FF9:

FF2, FF10:

FF25:

SAME AS FF1 EXCEPT Q IS BROUGHT OUT AND Q, Q GO TO TGf AND TGe RESP.

DELETE TGe, TGf, AND INVf; FEED Q TO D; DELETE CLEN, CLDIS

INVa AND INVd BECOME 2-INPUT NAND GATES, WITH ADDED INPUTS S; FEED Q

TO TGf VSS TO TGe PREVIOUS Q INPUT; DELETE Q OUTPUT