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CDP1020 Datasheet(PDF) 5 Page - Intersil Corporation |
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CDP1020 Datasheet(HTML) 5 Page - Intersil Corporation |
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5 / 23 page  2-422 Notational Conventions The following conventions are used throughout this document: • Hexadecimal numbers are denoted with a “$” symbol preceding the number. • Binary numbers are represented with a “%” symbol proceeding the number, or a “b” following. • Because of the large mix of active-low and active-high signals used in connection with the CDP1020, the terms “asserted” and “de-asserted” will be used exclusively. An active low signal is asserted when it is at a logic 0 and de- asserted when it is at a logic 1 state. Conversely, an active high signal is at a logic 1 state when asserted and at a logic 0 state when de-asserted. The terms reset, clear, and “low” can also mean logic 0; set or “high” can also mean logic 1. • Active low signals are represented with an overline; active high signals have no overline. For example, REMREQ0 is active low, PWREN0 is active high. • There are many pins, signals, registers, and software bits common to both Bay 0 and Bay 1; these names may include the Bay number suffix (0 or 1), an “x” to represent either, or no suffix at all. For example, PWREN, PWREN0, or PWRENx may each be used to describe output pin(s). SCK SDA STOP START START tHD:STA tLOW tHIGH tSU:STO STOP tHD:DAT tSU:DAT tSU:STA tHD:STA FIGURE 1. CONTROL TIMING tBUF Control Timing VDD = 3.3V ±10%, TA = 0 oC to 85oC PARAMETER SYMBOL MIN MAX UNITS Frequency Of Operation (4.0MHz nominal) (CLK Pin) fCLK 2.0 4.5 MHz Suspend Recovery Start-up Time tRSUS 0.9 1 ms RESET Pulse Width (RESET Pin) tRL 6- tOSC Input Debounce Time (1394PRx, USBPRx, REMREQx, SECUREx Pins) tDB 50 - ms SMBus SCK and SDA Pins SCK Frequency fSMB 10 100 kHz SMBus Free Time tBUF 4.7 - µs Hold Time After (Repeated) Start Condition tHD:STA 4.0 - µs Repeated Start Condition Setup Time tSU:STA 4.7 - µs Stop Condition Setup Time tSU:STO 4.0 - µs Data Hold Time tHD:DAT 300 - ns Data Setup Time tSU:DAT 250 - ns SCK Time-out Period tTIMEOUT 25 35 ms SCK Low Period tLOW 4.7 - µs SCK High Period tHIGH 4.0 50 µs Slave SCK Extend Period (cumulative) tLOW:SEXT -25 ms Master SCK Extend Period (cumulative) tLOW:MEXT -10 ms SCK/SMBDAT Fall Time tF - 300 ns SCK/SMBDAT Rise Time tR - 1000 ns CDP1020 |
Similar Part No. - CDP1020 |
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Similar Description - CDP1020 |
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