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AD8026 Datasheet(PDF) 6 Page - Analog Devices |
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AD8026 Datasheet(HTML) 6 Page - Analog Devices |
6 / 8 page AD8026 –6– REV. 0 FREQUENCY – Hz 100 10k 100M 100k 1M 10M 0.1 0.01 10 1 1G Figure 15. Output Impedance vs. Frequency FREQUENCY – Hz 1M 10k 100M 100k 1M 10M 1k 100 10k 1G 100k 10 Figure 16. Input Impedance vs. Frequency FREQUENCY – Hz 20 –10 –20 10 0 1 0 24.9 49.9 100 RS 3k 1875 + – CL 5k VIN = 50mV rms CL = 100pF 100k 1M 10M 100M 500M Figure 17. Bandwidth and Flatness vs. Series Resistance into 100 pF THEORY OF OPERATION The AD8026, a quad voltage feedback amplifier with rail-to-rail output swing, is internally configured for a gain of either –5/3 or +8/3. The gain-setting resistors are laser trimmed for precise control of their ratio. In addition, the amplifier’s frequency response has been adjusted to compensate for the parasitic capacitances associated with the gain resistors and with the amplifier’s inverting input. The result is an amplifier with very tight control of closed-loop gain and settling time. The amplifier’s input stage will operate with voltages from about –0.2 V below the negative supply voltage to within about 1 V of the positive supply. Exceeding these values will not cause phase reversal at the output; however, the input ESD protection de- vices will begin to conduct if the input voltages exceed the sup- ply rails by greater than 0.5 V. The gain resistors that connect to Pins 2, 6, 9, and 13 are protected from ESD in such a way that the voltages applied to these pins may exceed the negative sup- ply by as much as –7 V. The rail-to-rail output range of the AD8026 is provided by a complementary common-emitter output stage. The chosen circuit topology allows the outputs to source and sink 50 mA of output current and, with the use of an external series resistor, to achieve rapid settling time while driving capacitive loads within 0.5 V of the supply rails. Output Referred Offset Voltage The output referred offset voltage for a voltage feedback ampli- fier can be estimated with the following equation: VOOS = V IOS × 1+ R F / RG ()+ I OS × R F RG ()+ I B × R P − R F RG () () where: VOOS = output referred offset voltage, VIOS = input referred offset voltage, IOS = difference of the two input currents, IB = average of the two input currents, RP = total resistance in series with positive input, RF = 5 k Ω, R G = 3 k Ω for this part. This equation leads to the well known conclusion that, for a voltage feedback amplifier to maintain minimum output offset voltage, the value of RP should be selected to match the parallel combination of RF and RG. It should be noted that the AD8026 was designed for an assumed source impedance, of 500 Ω driv- ing the +Input. Therefore, the value of RP included on the chip is 500 Ω less than the ideal value for minimum output offset. Additional resistance may be added externally, in series with the +Input, if the part is to be driven by a lower impedance source. APPLICATIONS The AD8026 is designed with on-chip resistors for each op amp to provide accurate fixed gain and low output-referenced offset voltages. This can result in significant cost and board-space savings for systems that can take advantage of the AD8026 specifications. The part is actually trimmed in three steps. First, the supply current of the part is trimmed. Then the gain is accurately trimmed to specification. This trim adjusts the values of either the gain or feedback resistor for a ratio of 5 to 3. The final trim is for the offset voltage. For this trim, the –Input is connected to ground and the +Input is connected to ground via 500 Ω, while internal offset resistors are trimmed. |
Similar Part No. - AD8026_15 |
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Similar Description - AD8026_15 |
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