4-91

March 1997

Features

• Compatible with General Purpose and CDP1800

Series Microprocessor Systems

• Two 16-Bit Down Counters and Two 8-Bit Control

Registers

• 5 Modes Including a Versatile Variable-Duty Cycle

Mode

• Programmable Gate-Level Select

• Two-Complemented Output Pins for Each Counter-

Timer

• Software-Controlled Interrupt Output

• Addressable in Memory Space or CDP1800-Series I/O

Space

Description

The CDP1878C is a dual counter-timer consisting of two 16-

bit programmable down counters that are independently

controlled by separate control registers. The value in the reg-

isters determine the mode of operation and control func-

tions. Counters and registers are directly addressable in

memory space by any general industry type microproces-

sors, in addition to input/output mapping with the CDP1800

series microprocessors.

Each counter-timer can be configured in five modes with the

additional flexibility of gate-level control. The control regis-

ters in addition to mode formatting, allow software start and

stop, interrupt enable, and an optional read control that

allows a stable readout from the counters. Each counter-

timer has software control of a common interrupt output with

an interrupt status register indicating which counter-timer

has timed out.

In addition to the interrupt output, true and complemented

outputs are provided for each counter-timer for control of

peripheral devices.

This type is supplied in 28-lead dual-in-line ceramic pack-

ages (D suffix), and 28-lead dual-in-line plastic packages (E

suffix).

Pinout

CDP1878C

(DIP)

TOP VIEW

Ordering Information

PART

NUMBER

TEMP. RANGE

PACKAGE

PKG. NO.

CDP1878CE

E28.6

CDP1878CD

N28.6

INT

TAO

TAO

TAG

TACL

RD

IO/MEM

TPB/WR

TPA

CS

A0

A1

A2

DB6

DB5

DB4

DB3

DB1

TBO

TBO

TBG

TBCL

RESET

DB7

DB2

DB0

28

27

26

25

24

23

22

21

20

19

18

17

16

15

1

2

3

4

5

6

7

8

9

10

11

12

13

14

TABLE 1. MODE DESCRIPTION

MODE

FUNCTION

APPLICATION

1 Timeout

Outputs change when clock

decrements counter to “0”

Event counter

2 Timeout

Strobe

One clockwide output pulse

when clock decrements

counter to “0”

Trigger pulse

3 Gate-Con-

trolled One

Shot

Outputs change when clock

decrements counter to “0”.

Retriggerable

Time-delay

generation

4 Rate Generator Repetitive clockwide output

pulse

Time-base

generator

5 Variable-Duty

Cycle

Repetitive output with

programmed duty cycle

Motor control

File Number

1341.2

CDP1878C

CMOS Dual Counter-Timer

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

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