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DG188AP Datasheet(PDF) 6 Page - Intersil Corporation |
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DG188AP Datasheet(HTML) 6 Page - Intersil Corporation |
6 / 9 page 6 DG181 Series DUAL SPST - DG181/182 TEST CONDITIONS VIN “ON” = 0.8V All Channels VIN “OFF” = 2.0V All Channels NOTE: 1. Switch states are for logic “1” input = 2.0V. SPDT - DG187/188 TEST CONDITIONS VIN “ON” = 2.0V Channel 1 VIN “ON” = 0.8V Channel 2 VIN “OFF” = 2.0V Channel 2 VIN “OFF” = 0.8V Channel 1 NOTE: 1. Switch states are for logic “1” input = 2.0V. DUAL DPST - DG184/185 TEST CONDITIONS VIN “ON” = 2.0V All Channels VIN “OFF” = 0.8V All Channels NOTE: 1. Switch states are for logic “1” input = 2.0V. SPDT - DG190/191 TEST CONDITIONS VIN “ON” = 2.0V Channel 1 and 2 VIN “ON” = 0.8V Channel 3 and 4 VIN “OFF” = 2.0V Channel 3 and 4 VIN “OFF” = 0.8V Channel 1 and 2 NOTE: 1. Switch states are for logic “1” input = 2.0V. NOTES: 1. Switch output waveform shown for VS = constant with logic input waveform as shown. 2. VS may be + or - as per switching time test circuit. VO is the steady state output with switch on. Feedthrough via gate capacitance may result in spikes at leading and trailing edge of output waveform. Switching Time Test Circuits FIGURE 1. SWITCHING TIME TEST WAVEFORMS (Note 1) FIGURE 2. SWITCHING TIME TEST CIRCUIT (Note 2) 50% 90% 0V tOFF LOGIC INPUT SWITCH OUTPUT VS tON tR < 10ns tF < 10ns 90% SWITCH INPUT 3V 50% 0V VO S1 IN1 LOGIC INPUT GND tON, VS = +10V RL 1 k Ω CL 30 pF SWITCH OUTPUT +15V VCC -15V V- SWITCH INPUT 0V (REPEAT TEST FOR ALL CHANNELS) VO = VS RL RL + RDS(ON) D1 +5V VL tOFF, VS = -10V |
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