10

Waveforms

VALID DATA

VALID DATA

A2:0, D3:0

WR

LATCH

FIGURE 8. DIGITAL TIMING REQUIREMENTS

(EDGE MODE)

CE

DATA (N)

DATA (N + 1)

DATA (N + 2)

DATA (N)

DATA (N)

DATA (N)

DATA (N + 1)

DATA (N + 1)

DATA (N + 1)

DATA (N + 2)

WR

LATCH

MASTER REGISTER CONTENTS

SLAVE REGISTER CONTENTS

SLAVE REGISTER CONTENTS

FIGURE 9. PARALLEL PROGRAMMING MODE OPERATION (SER/PAR = 0)

DATA (N + 2)

DATA (N + 2)

(EDGE/LEVEL = 0)

(EDGE/LEVEL = 1)

SLAVE REGISTER CONTENTS

(EDGE/LEVEL = 0)

SLAVE REGISTER CONTENTS

(EDGE/LEVEL = 1)

WR

LATCH

NEW DATA

NEW DATA

NEW DATA FOR

OUT1 TO OUT6

NEW DATA FOR

OUT0

NEW DATA FOR

OUT7

D1

D2

D3

D0

D3

D2

D3

D2

D1

D0

FIGURE 10. SERIAL PROGRAMMING MODE OPERATION (SER/PAR = 1)

t = 0

1ST

WRITE

32ND

WRITE

OLD DATA

OLD DATA

SER IN

HA457