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AD8803 Datasheet(PDF) 2 Page - Analog Devices

Part # AD8803
Description  Octal 8-Bit TrimDAC with Power Shutdown
Download  16 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD8803 Datasheet(HTML) 2 Page - Analog Devices

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REV. A
–2–
Parameter
Symbol
Conditions
Min
Typ
1
Max
Units
STATIC ACCURACY
Specifications Apply to All DACs
Resolution
N
8
Bits
Integral Nonlinearity Error
INL
–1.5
±1/2
+1.5
LSB
Differential Nonlinearity
DNL
Guaranteed Monotonic
–1
±1/4
+1
LSB
Full-Scale Error
GFSE
–4
–2.8
+0.5
LSB
Zero-Code Error
VZSE
–0.5
±0.1
+0.5
LSB
DAC Output Resistance
ROUT
35
8
k
Output Resistance Match
∆R/R
O
1%
REFERENCE INPUT
Voltage Range
2
VREFH
0VDD
V
VREFL
Pin Available on AD8803 Only
0
VDD
V
Input Resistance
RREFH
Digital Inputs = 55H, VREFH = VDD
2k
Reference Input Capacitance
3
CREF0
Digital Inputs All Zeros
25
pF
CREF1
Digital Inputs All Ones
25
pF
DIGITAL INPUTS
Logic High
VIH
VDD = +5 V
2.4
V
Logic Low
VIL
VDD = +5 V
0.8
V
Logic High
VIH
VDD = +3 V
2.1
V
Logic Low
VIL
VDD = +3 V
0.6
V
Input Current
IIL
VIN = 0 V or +5 V
± 1
µA
Input Capacitance
3
CIL
5pF
POWER SUPPLIES
4
Power Supply Range
VDD Range
2.7
5.5
V
Supply Current (CMOS)
IDD
VIH = VDD or VIL = 0 V
0.01
5
µA
Supply Current (TTL)
IDD
VIH = 2.4 V or VIL = 0.8 V, VDD= +5.5 V
1
4
mA
Shutdown Current
IREFH
SHDN
= 0
0.01
5
µA
Power Dissipation
PDISS
VIH = VDD or VIL = 0 V, VDD = +5.5 V
27.5
µW
Power Supply Sensitivity
PSRR
VDD = 5 V ± 10%, VREFH = +4.5 V
0.001
0.002
%/%
Power Supply Sensitivity
PSRR
VDD = 3 V ± 10%, VREFH = +2.7 V
0.01
%/%
DYNAMIC PERFORMANCE
3
VOUT Settling Time (Positive or Negative)
tS
±1/2 LSB Error Band
0.6
µs
Crosstalk
CT
See Note 5, f = 100 kHz
50
dB
SWITCHING CHARACTERISTICS
3, 6
Input Clock Pulse Width
tCH, tCL
Clock Level High or Low
15
ns
Data Setup Time
tDS
5ns
Data Hold Time
tDH
5ns
CS
Setup Time
tCSS
10
ns
CS
High Pulse Width
tCSW
10
ns
Reset Pulse Width
tRS
60
ns
CLK Rise to CS Rise Hold Time
tCSH
15
ns
CS
Rise to Next Rising Clock
tCS1
10
ns
NOTES
1Typical values represent average readings measured at +25
°C.
2V
REFH can be any value between GND and V DD, for the AD8803 VREFL can be any value between GND and V DD.
3Guaranteed by design and not subject to production test.
4Digital Input voltages V
IN = 0 V or VDD for CMOS condition. DAC outputs unloaded. PDISS is calculated from (IDD × VDD).
5Measured at a V
OUT pin where an adjacent VOUT pin is making a full-scale voltage change.
6See timing diagram for location of measured values. All input control voltages are specified with t
R = tF = 2 ns (10% to 90% of VDD) and timed from a voltage
level of 1.6 V.
Specifications subject to change without notice.
AD8801/AD8803–SPECIFICATIONS
(VDD = +3 V
10% or +5 V
10%, VREFH = +VDD, VREFL = 0 V, –40 C
≤ T
A
≤ +85 C unless otherwise noted)


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