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HCS166DMSR Datasheet(PDF) 2 Page - Intersil Corporation |
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HCS166DMSR Datasheet(HTML) 2 Page - Intersil Corporation |
2 / 9 page 251 HCS166MS Functional Diagram TRUTH TABLE INPUTS INTERNAL Q STATES OUTPUT Q7 MASTER RESET PARALLEL ENABLE CLOCK ENABLE CLOCK SERIAL PARALLEL D0 - D7 Q0 Q1 L X XXX X L L L H X L L X X Q00 Q10 Q0 H L L X a . . . h a b h H H L H X H Q0n Q6n H H L L X L Q0n Q6n H X H X X Q00 Q10 Q70 H = High Level L = Low Level X = Immaterial = Transition from low to high level a . . . h = The level of steady state input at inputs D0 thru D7, respectively. Q00, Q10, Q70 = The level of Q0, Q1, or Q7, respectively, before the indicated steady state input conditions were established. Q0n, Q6n = the level of Q0 or Q6, respectively, before the most recent transition of the clock. MR CE DS PE CP Q7 D2 D0 D3 D5 D6 D7 D4 D1 Spec Number 518758 |
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