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HCTS244T Datasheet(PDF) 3 Page - Intersil Corporation |
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HCTS244T Datasheet(HTML) 3 Page - Intersil Corporation |
3 / 3 page 3 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with- out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Die Characteristics DIE DIMENSIONS: (2743 µm x 2692µm x 533µm ±51µm) 108 x 106 x 21mils ±2mil METALLIZATION: Type: Al Si Thickness: 11.0k Å ±1kÅ SUBSTRATE POTENTIAL: Unbiased Silicon on Sapphire BACKSIDE FINISH: Sapphire PASSIVATION: Type: Silox (SiO2) Thickness: 13.0k Å ±2.6kÅ WORST CASE CURRENT DENSITY: < 2.0e5 A/cm2 TRANSISTOR COUNT: 264 PROCESS: CMOS SOS Metallization Mask Layout HCTS244T 1OE (1) 2OE (19) VCC (20) 1A0 (2) 1A1 (4) 2Y3 (3) 2Y2 (5) 1A2 (6) 2Y1 (7) (8) (9) (10) (11) (12) (13) 1A3 2Y0 GND 2A0 1Y3 2A1 (14) 1Y2 (15) 2A2 (16) 1Y1 (17) 2A3 (18) 1Y0 NOTE: The die diagram is a generic plot from a similar HCS device. It is intended to indicate approximate die size and bond pad location. The mask series for the HCTS244 is TA14402A. HCTS244T |
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