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AD9761 Datasheet(PDF) 3 Page - Analog Devices

Part # AD9761
Description  Dual 10-Bit TxDAC
Download  24 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9761 Datasheet(HTML) 3 Page - Analog Devices

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–2–
AD9761–SPECIFICATIONS
AD9761
–3–
DYNAMIC SPECIFICATIONS
(TMIN to TMAX, AVDD = 5 V, DVDD = 5 V, IOUTFS = 10 mA, Differential Transformer Coupled Output,
50  Doubly Terminated, unless otherwise noted.)
DIGITAL SPECIFICATIONS (T
MIN to TMAX, AVDD = 5 V, DVDD = 5 V, IOUTFS = 10 mA unless otherwise noted.)
Parameter
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
Maximum Output Update Rate
40
MSPS
Output Settling Time (tST to 0.025%)
35
ns
Output Propagation Delay (tPD)
55
Input Clock Cycles
Glitch Impulse
5
pV-s
Output Rise Time (10% to 90%)
2.5
ns
Output Fall Time (10% to 90%)
2.5
ns
AC LINEARITY TO NYQUIST
Signal-to-Noise and Distortion (SINAD)
fOUT = 1 MHz; CLOCK = 40 MSPS
56
59
dB
Effective Number of Bits (ENOBs)
9.0
9.5
Bits
Total Harmonic Distortion (THD)
fOUT = 1 MHz; CLOCK = 40 MSPS
TA = 25°C
–68
–58
dB
TMIN to TMAX
–67
–53
dB
Spurious-Free Dynamic Range (SFDR)
fOUT = 1 MHz; CLOCK = 40 MSPS; 10 MHz Span
59
68
dB
Channel Isolation
fOUT = 8 MHz; CLOCK = 40 MSPS; 10 MHz Span
90
dBc
Specifications subject to change without notice.
Parameter
Min
Typ
Max
Unit
DIGITAL INPUTS
Logic 1 Voltage @ DVDD = 5 V
3.5
5
V
Logic 1 Voltage @ DVDD = 3 V
2.4
3
V
Logic 0 Voltage @ DVDD = 5 V
0
1.3
V
Logic 0 Voltage @ DVDD = 3 V
0
0.9
V
Logic 1 Current
–10
+10
µA
Logic 0 Current
–10
+10
µA
Input Capacitance
5
pF
Input Setup Time (tS)
3
ns
Input Hold Time (tH)
2
ns
CLOCK High
5
ns
CLOCK Low
5
ns
Invalid CLOCK/WRITE Window (tCINV)*
1
5
ns
*tCINV is an invalid window of 4 ns duration beginning 1 ns after the rising edge of WRITE in which the rising edge of CLOCK must not occur.
Specifications subject to change without notice.
I DATA
Q DATA
tCINV
DB9–DB0
DAC
INPUTS
SELECT
WRITE
CLOCK
tS
tH
NOTE: WRITE AND CLOCK CAN BE
TIED TOGETHER. FOR TYPICAL EXAMPLES,
REFER TO DIGITAL INPUTS AND INTERLEAVED
INTERFACE CONSIDERATION SECTION.
Figure 1.Timing Diagram
REV. C
REV. C


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