AD9823

Rev. 0 | Page 7 of 8

CCD

SIGNAL

EFFECTIVE PIXELS

CLP

OPTICAL BLACK PIXELS

HORIZONTAL

BLANKING

DUMMY PIXELS

EFFECTIVE PIXELS

Figure 4. CLP Timing

14

13

12

11

10

9

8

1

2

3

4

5

6

7

AD9823

TOP VIEW

(Not to Scale)

NC

NC = NO CONNECT

CLP

VDD

SHP

SHD

REFOUT

GND

CCDIN

DATAOUT

GND

NC

BYP1

BYP3

BYP2

3V

ANALOG

SUPPLY

4.7

µF

0.1

µF

SHP

SHD

CCDIN

CLP

REFOUT

(CONNECT TO VIN– ON AD9821)

DATAOUT

(CONNECT TO VIN+ ON AD9821)

0.1

µF

0.1

µF

0.1

µF

0.1

µF

Figure 5. AD9823 Circuit Configuration

14

13

12

11

8

9

10

1

2

3

4

5

6

7

AD9823

TOP VIEW

(Not to Scale)

NC

CLP

VDD

SHP

SHD

REFOUT

GND

CCDIN

DATAOUT

GND

NC

BYP1

BYP3

BYP2

OUTPUT

FROM

CCD

SHD

SHP

36

35

34

33

32

31

30

29

28

27

26

25

13 14 15 16 17 18 19 20 21 22 23 24

1

2

3

4

5

6

7

8

9

10

11

12

37

48 47 46 45 44

39 38

43 42 41 40

PIN 1

IDENTIFIER

TEST

AVSS

TEST

AVDD2

BYP1

VIN–

VIN+

TEST

TEST

AVDD1

AVSS

AVSS

D0

D1

D2

D3

D4

D5

D6

D7

D8

(MSB) D11

AD9821

TOP VIEW

(Not to Scale

3V

ANALOG SUPPLY

12

DATA

OUTPUTS

3

SERIAL

INTERFACE

3V

ANALOG SUPPLY

3

CLOCK

INPUTS

3V

ANALOG SUPPLY

3V

DRIVER

SUPPLY

NC = INTERNALLY NOT CONNECTED

D9

D10

IMAGER INPUT, NEGATIVE

IMAGER INPUT, POSITIVE

CLP

3V

ANALOG SUPPLY

3V

ANALOG SUPPLY

0.1

µF

0.1

µF

0.1

µF

1.0

µF

1.0

µF

0.1

µF

0.1

µF

0.1

µF

0.1

µF

0.1

µF

0.1

µF

0.1

µF

0.1

µF

4.7

µF

4.7

µF

Figure 6. Circuit Configuration with the AD9821 12-Bit Image Signal Processor