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AD9846A Datasheet(PDF) 9 Page - Analog Devices |
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AD9846A Datasheet(HTML) 9 Page - Analog Devices |
9 / 24 page REV. 0 AD9846A –9– CCD-MODE AND AUX MODE TIMING N N+1 N+2 N+9 N+10 tID tID tS1 tS2 tCP tINH tOD tH N–10 N–9N–8N–1N NOTES: 1. RECOMMENDED PLACEMENT FOR DATACLK RISING EDGE IS BETWEEN THE SHD RISING EDGE AND NEXT SHP FALLING EDGE. 2. CCD SIGNAL IS SAMPLED AT SHP AND SHD RISING EDGES. SHP SHD DATACLK OUTPUT DATA CCD SIGNAL Figure 5. CCD-Mode Timing CCD SIGNAL EFFECTIVE PIXELS CLPOB CLPDM OPTICAL BLACK PIXELS HORIZONTAL BLANKING DUMMY PIXELS EFFECTIVE PIXELS PBLK NOTES: 1. CLPOB AND CLPDM WILL OVERWRITE PBLK. PBLK WILL NOT AFFECT CLAMP OPERATION IF OVERLAPPING CLPDM AND/OR CLPOB. 2. PBLK SIGNAL IS OPTIONAL. 3. DIGITAL OUTPUT DATA WILL BE ALL ZEROS DURING PBLK. OUTPUT DATA LATENCY IS 9 DATACLK CYCLES. OUTPUT DATA EFFECTIVE PIXEL DATA OB PIXEL DATA DUMMY BLACK EFFECTIVE DATA Figure 6. Typical CCD-Mode Line Clamp Timing DATACLK OUTPUT DATA VIDEO SIGNAL N N+1 N+2 N+8 N+9 N–10 N–9N–8N–1N tID tCP tOD tH N+10 Figure 7. AUX-Mode Timing |
Similar Part No. - AD9846A_15 |
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Similar Description - AD9846A_15 |
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