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AD9878 Datasheet(PDF) 8 Page - Analog Devices

Part # AD9878
Description  Mixed-Signal Front End for Broadband Applications
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9878 Datasheet(HTML) 8 Page - Analog Devices

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AD9878
Rev. A | Page 8 of 36
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
REFT10
75
REFB10
74
AGND10
73
AVDD10
72
DRVDD
71
DRGND
70
REFCLK
69
SIGDELT
68
FLAG1
67
FLAG2
66
CA_EN
65
CA_DATA
64
CA_CLK
63
DVDDOSC
62
OSCIN
61
XTAL
60
DGNDOSC
59
AGNDPLL
58
PLLFILT
57
AVDDPLL
56
DVDDPLL
55
DGNDPLL
54
AVDDTx
53
Tx+
52
Tx–
51
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
DRGND
1
DRVDD
2
(MSB) IF12(11)
3
IF12(10)
4
IF12(9)
5
IF12(8)
6
IF12(7)
7
IF12(6)
8
IF12(5)
9
IF12(4) 10
IF12(3) 11
IF12(2) 12
IF12(1) 13
IF12(0) 14
(MSB) IF10(4) 15
IF10(3) 16
IF10(2) 17
IF10(1) 18
IF10(0) 19
RxSYNC 20
DRGND 21
DRVDD 22
MCLK 23
DVDD 24
DGND 25
AD9878
TOP VIEW
(Not to Scale)
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
Descriptions
1, 21, 70
DRGND
Pin Driver Digital Ground
2, 22, 71
DRVDD
Pin Driver Digital 3.3 V Supply
3
(MSB) IF12(11)
12-Bit ADC Digital Ouput
4 to 14
IF12[10:0]
12-Bit ADC Digital Ouput
15
(MSB) IF10(4)
10-Bit ADC Digital Ouput
16 to 19
IF10[3:0]
10-Bit ADC Digital Ouput
20
RxSYNC
Sync Output, 10-Bit and 12-Bit ADCs
23
MCLK
Master Clock Output
24, 33, 35, 39
DVDD
Digital 3.3 V Supply
25, 34, 36, 40
DGND
Digital Ground
26
TxSYNC
Sync Input for Transmit Port
27
(MSB) TxIQ(5)
Digital Input for Transmit Port
28 to 32
TxIQ[4:0]
Digital Input for Transmit Port
37
PROFILE
Profile Selection Input
38
RESET
Chip Reset Input
41
SCLK
SPORT Clock
42
CS
SPORT Chip Select
43
SDIO
SPORT Data I/O


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