AD14060/AD14060L

Rev. B | Page 10 of 48

SYNCHRONOUS READ/WRITE—BUS MASTER

Use these specifications for interfacing to external memory systems that require CLKIN—relative timing or for accessing a slave

ADSP 2106x in multiprocessor memory space. These synchronous switching characteristics are also valid during asynchronous memory

reads and writes (see the Memory Read—Bus Master and Memory Write—Bus Master sections).

When accessing a slave ADSP-2106x, these switching characteristics must meet the slave’s timing requirements for synchronous

read/writes (see the Synchronous Read/Write—Bus Slave section). The slave ADSP-2106x must also meet these bus master timing

requirements for data and acknowledge setup and hold times.

Table 10. Specifications

5 V

3.3 V

Parameter

Min

Max

Min

Max

Unit

Timing Requirements:

Data Setup before CLKIN

3 + DT/8

3 + DT/8

ns

Data Hold after CLKIN

4 − DT/8

4 − DT/8

ns

ACK Delay after Address, MSx, SW, BMS1, 2

13.5 + 7 DT/8 + W

13.5 + 7 DT/8 + W

ns

ACK Setup before CLKIN2

6.5 + DT/4

6.5 + DT/4

ns

ACK Hold after CLKIN

−0.5 − DT/4

−0.5 − DT/4

ns

Switching Characteristics:

Address, MSx, BMS, SW, Delay after CLKIN1

8 − DT/8

8 − DT/8

ns

Address, MSx, BMS, SW, Hold after CLKIN

−1 − DT/8

−1 − DT/8

ns

PAGE Delay after CLKIN

9 + DT/8

17 + DT/8

9 + DT/8

17 + DT/8

ns

RD High Delay after CLKIN

−2 − DT/8

+5 − DT/8

−2 − DT/8

+5 − DT/8

ns

WR High Delay after CLKIN

−3 − 3 DT/16

+5 − 3 DT/16

−3 − 3 DT/16

+5 − 3 DT/16

ns

RD/WR Low Delay after CLKIN

8 + DT/4

13.5 + DT/4

8 + DT/4

13.5 + DT/4

ns

Data Delay after CLKIN

20 + 5 DT/16

20.25 + 5 DT/16

ns

Data Disable after CLKIN3

0 − DT/8

8 − DT/8

0 − DT/8

8 – DT/8

ns

ADRCLK Delay after CLKIN

4 + DT/8

11 + DT/8

4 + DT/8

11 + DT/8

ns

ADRCLK Period

ns

ADRCLK Width High

ns

ADRCLK Width Low

ns

section for the calculation of hold times given capacitive and dc loads.

System Hold Time Calculation Example