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HI1866 Datasheet(PDF) 3 Page - Intersil Corporation |
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HI1866 Datasheet(HTML) 3 Page - Intersil Corporation |
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3 / 13 page  4-3 Pin Descriptions PIN NO. SYMBOL I/O TYPICAL VOLTAGE LEVEL EQUIVALENT CIRCUIT DESCRIPTION 21 VRT I 0V Top reference voltage input (= 0). This is the top reference voltage supplied to the internal resistance chain. The external input can be set in accordance with the peak value on the plus side of the input analog signal amplitude. 22 VRTS O0V VRT sense output. This is the voltage sense pin for VRT. 16 VRB I -2V Bottom reference voltage input (= -2V). This is the bottom reference voltage supplied to the internal resistance chain. The external input can be set in accordance with the peak value on the minus side of the input analog signal amplitude. 15 VRBS O -2V VRB sense output. This is the voltage sense pin for VRB. 19 VIN IVRTS to VRBS Analog input. The input range is 2VP-P. 26 CCLK I ECL CCLK clock input. This is the conversion clock, and is an ECL level input. 25 NCCLK I ECL CCLK inversion clock input. This is an ECL level input. When left open, this input goes to the ECL threshold potential (-1.3V). Only CCLK input can be used for operation with the NCCLK input left open, but complementary input is recommended to attain fast and stable operation. 11 DCLK I ECL DCLK clock input. This is the 1:2 DMPX latch clock; input a clock of 1/2 frequency of CCLK. Data is output from DMPX port 1 and port 2 synchronously with the rising edge of this signal. This is an ECL level input. 12 NDCLK I ECL DCLK inversion clock input. This is an ECL level input. When left open, this input goes to the ECL threshold potential (-1.3V). Only DCLK input can be used for operation with the NDCLK input left open, but complementary input is recommended to attain fast and stable operation. VRT VRTS VRBS VRB COMPARATOR 1 COMPARATOR 2 COMPARATOR 31 COMPARATOR 32 COMPARATOR 63 VIN AGND AVEE DGND1 CCLK (DCLK) NCCLK (NDCLK) 500 500 DVEE 1.3V R R R R RR HI1866 |
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