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HI1-674AKD-5 Datasheet(PDF) 8 Page - Intersil Corporation

Part # HI1-674AKD-5
Description  Complete, 12-Bit A/D Converters with Microprocessor Interface
Download  18 Pages
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Manufacturer  INTERSIL [Intersil Corporation]
Direct Link  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

HI1-674AKD-5 Datasheet(HTML) 8 Page - Intersil Corporation

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background image
6-959
tHEC
CE Pulse Width
50
-
-
ns
tSSC
CS to CE Setup
50
-
-
ns
tHSC
CS Low During CE High
50
-
-
ns
tSRC
R/C to CE Setup
50
-
-
ns
tHRC
R/C Low During CE High
50
-
-
ns
tSAC
AO to CE Setup
0
-
-
ns
tHAC
AO Valid During CE High
50
-
-
ns
tC
Conversion Time
12-Bit Cycle TMIN to TMAX
15
20
25
µs
8-Bit Cycle TMIN to TMAX
10
13
17
µs
READ MODE
tDD
Access Time from CE
-
75
150
ns
tHD
Data Valid After CE Low
25
-
-
ns
tHL
Output Float Delay
-
100
150
ns
tSSR
CS to CE Setup
50
-
-
ns
tSRR
R/C to CE Setup
0
-
-
ns
tSAR
AO to CE Setup
50
-
-
ns
tHSR
CS Valid After CE Low
0
-
-
ns
tHRR
R/C High After CE Low
0
-
-
ns
tHAR
AO Valid After CE Low
50
-
-
ns
tHS
STS Delay After Data Valid
300
-
1200
ns
Timing Specifications (HI-674A) 25oC, Note 2, Unless Otherwise Specified
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
CONVERT MODE
tDSC
STS Delay from CE
-
-
200
ns
tHEC
CE Pulse Width
50
-
-
ns
tSSC
CS to CE Setup
50
-
-
ns
tHSC
CS Low During CE High
50
-
-
ns
tSRC
R/C to CE Setup
50
-
-
ns
tHRC
R/C Low During CE High
50
-
-
ns
tSAC
AO to CE Setup
0
-
-
ns
tHAC
AO Valid During CE High
50
-
-
ns
tC
Conversion Time
12-Bit Cycle TMIN to TMAX
912
15
µs
8-Bit Cycle TMIN to TMAX
68
10
µs
READ MODE
tDD
Access Time from CE
-
75
150
ns
tHD
Data Valid After CE Low
25
-
-
ns
tHL
Output Float Delay
-
100
150
ns
Timing Specifications (HI-574A) 25oC, Note 2, Unless Otherwise Specified (Continued)
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
HI-574A, HI-674A, HI-774


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