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HI20201JCB Datasheet(PDF) 3 Page - Intersil Corporation |
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HI20201JCB Datasheet(HTML) 3 Page - Intersil Corporation |
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3 / 11 page  10-1199 Absolute Maximum Ratings Thermal Information Digital Supply Voltage DVEE to DVSS . . . . . . . . . . . . . . . . . . . -7.0V Analog Supply Voltage AVDD to AVSS . . . . . . . . . . . . . . . . . . -7.0V Digital Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 to DVEE V Reference Input Voltage . . . . . . . . . . . . . . . . . . . . . . +0.3 to AVEE V Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA Thermal Resistance (Typical, Note 1) θ JA ( oC/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Recommended Operating Conditions Supply Voltage AVEE,DVEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . -4.75V to -5.45V AVEE - DVEE. . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.05V to +0.05V Digital Input Voltage VIH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to -0.7V VIL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.9V to -1.6V Reference Input Voltage, VREF . . . . . . . . VEE + 0.5V to VEE + 1.4V Load Resistance, RL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≥75Ω Output Voltage, VOUT . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8V to 1.2V Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . .-20oC to 75oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications TA = 25 oC, AV EE = DVEE = -5.2V, AGND = DGND = 0V, RL = ∞, VOUT = -1V PARAMETER TEST CONDITIONS HI20201JCB/JCP UNITS MIN TYP MAX SYSTEM PERFORMANCE Resolution 10 - - Bits Integral Linearity Error, INL fS = 160MHz (End Point) - - ±1.0 LSB Differential Linearity Error, DNL fS = 160MHz - - ±0.50 LSB Offset Error, VOS (Adjustable to Zero) (Note 3) - 7 - LSB Full Scale Error, FSE (Adjustable to Zero) (Note 3) - - ±102 LSB Full Scale Output Current, IFS - - 20 mA DYNAMIC CHARACTERISTICS Throughput Rate See Figure 11 160 - - MHz Glitch Energy, GE ROUT = 75Ω - 15 - pV/s REFERENCE INPUT Voltage Reference Input Range With Respect to AVEE +0.5 - +1.4 V Reference Input Current VREF = -4.58V -0.1 -0.4 -3.0 µA Voltage Reference to Output Small Signal Bandwidth -3dB point 1VP-P Input - 14.0 - MHz Output Rise Time, tr RLOAD = 75Ω - 1.5 - ns Output Fall Time, tf RLOAD = 75Ω - 1.5 - ns DIGITAL INPUTS Input Logic High Voltage, VIH (Note 2) -1.0 -0.89 V Input Logic Low Voltage, VIL (Note 2) -1.75 -1.6 V Input Logic Current, IIL, IIH (For D9 thru D6, COMPL) VIH = -0.89V, VIL = -1.75V (Note 2) 0.1 1.5 6.0 µA Input Logic Current, IIL, IIH (For D5 thru D0) VIH = -0.89V, VIL = -1.75V (Note 2) 0.1 0.75 3.0 µA TIMING CHARACTERISTICS Data Setup Time, tSU See Figure 11 5 - - ns Data Hold Time, tHLD See Figure 11 1 - - ns Propagation Delay Time, tPD See Figure 11 - 3.8 - ns Settling Time, tSET (to 1/ 2 LSB) See Figure 11 - 5.2 - ns HI20201 |
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