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HI20206 Datasheet(PDF) 11 Page - Intersil Corporation |
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HI20206 Datasheet(HTML) 11 Page - Intersil Corporation |
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11 / 13 page  10-11 (2) Phase Relationship Between Data and Clock In order to obtain the desired characteristics as a D/A converter, it is necessary to set the phase relationship correctly between the externally applied data and clock. Satisfy the standard of the set-up time (tS) and hold time (tH) indicated in the electrical characteristics. As to the meaning of tS and tH, see the timing chart. Moreover, the clock pulse width is desired to be as indicated in the recommended operating condition. (3) Regarding the Load of D/A Output Pin Receive the D/A output of the next stage with high impedance. In other words perform so that it becomes as follows: RL > 10kΩ CL < 20pF. The temperature characteristics indicated in the characteristics diagram has been measured under this condition. However, when it is made RL ≤ 10kΩ the temperature characteristics may change considerably. In addition, when it is made to CL ≥ 20pF, the rise and fall of the D/A output become slow and will not operate at high speed. (4) Noise Reduction Measures As the D/A output voltage is a minute voltage of approximately 4mV per one step, ingenuity is required in reducing the noise entering from the outside of the IC as much as possible. Therefore, use the items given below as reference. • When mounting onto the printed board, allow as much space as possible to the ground surface and the VCC surface on the board and reduce the para- sitic inductance and resistance. • It is desirable that the AGND and DGND be sepa- rated in the pattern on the board. It is similar with AVCC and DVCC. As shown in the diagram below, for example, it is recommended that the wiring to the electric supply of AGND and DGND as also AVCC and DVCC be conducted separately, and then mak- ing AGND and DGND as also AVCC and DVCC in common right near the power supply respectively. • Insert in parallel a 47 µF tantalum capacitor and a 100pF ceramic capacitor between the VCC surface on the printed board and the nearmost ground sur- face. (A of diagram below). It is also desirable to insert the above between the VCC surface near the pin of the IC and the ground surface (see Figure 11). They are bypass capacitors to prevent bad effects from occurring to the characteristics when the power supply voltage fluctuates due to the clock, etc. It is recommended to reduce noise which overlaps the D/A output by inserting a capacitor of over 0.1 µF between pin 25 (AGND) and pin 26 (VSET). PRINTED BOARD HI20206 POWER SUPPLY DGND AGND AVCC DVCC A B FIGURE 11. HI20206 |
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