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HI3246 Datasheet(PDF) 9 Page - Intersil Corporation |
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HI3246 Datasheet(HTML) 9 Page - Intersil Corporation |
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9 / 16 page  9 Notes on Operation • The HI3246 is a high-speed A/D converter which is capable of TTL, ECL and PECL level clock input. Characteristic impedance should be properly matched to ensure optimum performance during high-speed operation. • The power supply and grounding have a profound influence on converter performance. The power supply and grounding method are particularly important during high- speed operation. General points for caution are as follows: - The ground pattern should be as large as possible. It is recommended to make the power supply and ground patterns wider at an inner layer using a multi-layer board. - To prevent interference between AGND and DGND and between AVCC and DVCC, make sure the respective patterns are separated. To prevent a DC offset in the power supply pattern, connect the AVCC and DVCC lines at one point each, via a ferrite-bead filter. Shorting the AGND and DGND patterns in one place immediately under the A/D converter improves A/D converter performance. - Ground the power supply pins (AVCC,DVCC1,DVCC2, DVEE3) as close to each pin as possible with a 0.1µF or larger ceramic chip capacitor. (Connect the AVCC pin to the AGND pattern and the DVCC1, DVCC2, DVEE3 pins to the DGND pattern). - The digital output wiring should be as short as possible. If the digital output wiring is long, the wiring capacitance will increase, deteriorating the output slew rate and resulting in reflection to the output waveform since the original output slew rate is quite fast. • The analog input pin VIN has an input capacitance of approximately 21pF. To drive the A/D converter with proper frequency response, it is necessary to prevent performance deterioration due to parasitic capacitance or parasitic inductance by using a large capacity drive circuit; keeping wiring as short as possible, and using chip parts for resistors and capacitors, etc. • The VRT and VRB pins must have adequate bypass to protect them from high-frequency noise. Bypass them to AGND with approximately 1 µF tantal capacitor and, 0.1µF capacitor. At this time, approximately DGND3 - 1.2V voltage is generated. However, this is not recommended for use as threshold voltage VBB as it is too weak. When the digital input level is PECL level, ***/E pins should be used and ***/T pins left open. When the digital input level is TTL, ***/T pins should be used and III/E pins left open. TABLE 1. A/D CODE VIN STEP INV 10 D7 D0 D7 D0 VRT 255 1111111100000000 254 1111111000000001 • • • • • • • • • VRM2 128 1000000001111111 127 0111111110000000 • • • • • • • • • 1 0 000000111111110 VRB 0 0 000000011111111 Test Circuits FIGURE 4. CURRENT CONSUMPTION MEASUREMENT CIRCUIT FIGURE 5. INTEGRAL LINEARITY ERROR/DIFFERENTIAL LINEARITY ERROR MEASUREMENT CIRCUIT VRT VIN VRB AVCC DVCC1 DVCC2 DGND2 DGND1 AGND DGND3 CLK/E DVEE3 4V 1.95V 2V 5MHz PECL A A 5V 5V ICC IEE A < B A > B COMPARATOR A8 TO A1 B8 TO B1 B0 A0 HI3246 BUFFER CONTROLLER DVM 000...00 TO 111..10 VIN 8 “0” 8 “1” -V +V S2 S1: ON WHEN A < B S2: ON WHEN A > B S1 - + HI3246 |
Similar Part No. - HI3246 |
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Similar Description - HI3246 |
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