Electronic Components Datasheet Search
Selected language     English  ā–¼


HI5634 Datasheet(PDF) 5 Page - Intersil Corporation

Part No. HI5634
Description  High Performance Programmable Phase-Locked Loop for LCD Applications
Download  16 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
Logo 

 
 5 page
background image
5
Application Information
Overview
The HI5634 addresses stringent graphics system line locked
and genlocked applications and provides the clock signals
required by high-performance video A/D converters. Included
are a phase locked loop (PLL) with a 500MHz voltage
controlled oscillator (VCO), a digital phase adjustment to
provide a user programmed pixel clock delay, the means for
deMUXing multiplexed A/D Converters, and both balanced
programmable (PECL) and single-ended (SSTL_3) high-speed
clock outputs.
Phase-Locked Loop
The phase-locked loop is optimized for line-locked
applications, for which the inputs are horizontal sync signals.
A high-performance Schmitt trigger preconditions the
HSYNC input, whose pulses can be degraded if they are
from a remote source. This preconditioned HSYNC signal is
provided as a clean reference signal with a short transition
time (in contrast, the signal that a typical PC graphics card
provides has a transition time of tens of nanoseconds).
A second high frequency input such as a crystal oscillator
and a 7-bit programmable divider can be selected. This
selection allows the loop to operate from a local source and
is also useful for evaluating intrinsic jitter.
A 12-bit programmable feedback divider completes the loop.
Designers can substitute an external divider.
Either the conditioned HSYNC input or the loop output
(recovered HSYNC) is available at the FUNC pin, aligned to
the edge of the pixel clock.
Automatic Power-On-Reset Detection
The HI5634 has automatic power-on-reset detection circuitry
and it resets itself if the supply voltage drops below threshold
values. No external connection to a reset signal is required.
Digital Phase Adjustment
The digital phase adjustment allows addition of a
programmable delay to the pixel clock output, relative to the
recovered HSYNC signal. The ability to add delays is
particularly useful when multiple video sources must be
synchronized. A delay of up to one pixel clock period is
selectable in the following increments:
1/64 period for pixel clock rates to 40MHz
1/32 period for pixel clock rates to 80MHz
1/16 period for pixel clock rates to 160MHz
Output Drivers and Logic Inputs
The HI5634 utilizes low voltage TTL (LVTTL) inputs as well
as SSTL_3 (EIA/JESD8-8) and low voltage PECL (pseudo-
ECL) outputs, operating at 3.3V supply voltage. The LVTTL
inputs are 5V tolerant. The SSTL_3 and differential PECL
output drivers drive resistive terminations or transmission
lines. At lower clock frequencies, the SSTL_3 outputs can be
operated unterminated.
I 2C-bus Serial Interface
The HI5634 utilizes the industry standard I2C-bus serial
interface. The interface uses 12 registers: one write-only,
eight read/write, and three read-only. Two HI5634 devices
can be addressed, according to the state of the I2 CADR pin.
When the pin is low, the read address is 4Dh, and the write
address is 4Ch. When the pin is high, the read address is
4Fh, and the write address is 4Eh. The I2C-bus serial
interface can run at either low speed (100kHz) or high speed
(400kHz) and provides 5V tolerant input.
PC Board Layout
Use a PC board with at least four layers: one power, one
ground, and two signal. No special cutouts are required for
power and ground planes. All supply voltages must be
supplied from a common source and must ramp up together.
Flux and other board surface debris can degrade the
performance of the external loop ļ¬lter. Ensure that the
HI5634 area of the board is free of contaminants.
PECL Clock Duty Cycle
t2, t3
45
50
55
%
PECL Clock to SSTL Clock Delay
t4
0.2
0.75
1.2
ns
PECL Clock to FUNC Delay
t5
1.5
1.9
2.3
ns
PECL Clock to PECL Clock/2 Delay
t6
1.0
1.3
1.5
ns
PECL Clock to SSTL Clock/2 Delay
t7
1.1
1.4
1.8
ns
SSTL Clock Duty Cycle
t8, t9
45
50
55
%
NOTES:
4. VOL must not fall below the minimum specified level or the IOUT value may not be maintained.
5. Measured at 3.6V 0oC, 135MHz output frequency, PECL Clock lines to 75
ā„¦ termination, SSTL Clock lines unterminated, 20pF load. Transition
times vary based on termination. See the ā€œOutput Timing Diagramā€ for details.
Electrical Speciļ¬cations
Per Operating Conditions Listed Above, Unless Otherwise Speciļ¬ed (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
HI5634




Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16 


Datasheet Download



Related Electronics Part Number

Part NumberComponents DescriptionHtml ViewManufacturer
HC2509CPhase-Locked Loop Clock Distribution for Synchronous DRAM Applications 1 2 3 4 5 MoreHynix Semiconductor
HC2510CPhase-Locked Loop Clock Distribution for Synchronous DRAM Applications 1 2 3 4 5 MoreHynix Semiconductor
HHBA-5218Low Profile 2 Gb/s Fibre Channel Adapters for High Performance Applications 1 2 3 4 Agilent(Hewlett-Packard)
NTE388Silicon Complementary Transistors General Purpose High Power Audio Disk Head Positioner for Linear Applications 1 2 NTE Electronics
NTE7069Integrated Circuit 2 Modulus High Speed Divider w/ECL Output for Phase-Lock Loop PLL Synthesized TV Tuner 1 2 NTE Electronics
2SC5150NPN TRIPLE DIFFUSED MESA TYPE HORIZONTAL DEFLECTION OUTPUT FOR GIHG RESOLUTION DISPLAY COLOR TV. HIGH SPEED SWITCHING APPLICATIONS 1 2 3 4 Toshiba Semiconductor
MACH4High Performance E 2 CMOS In-System Programmable Logic 1 2 3 4 5 MoreLattice Semiconductor
KS57C21832The KS57C21832 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core SAM47 Samsung Arrangeabl 1 2 3 4 5 MoreSamsung semiconductor
2N2857CSMHIGH FREQUENCY NPN TRANSISTOR IN A HERMETICALLY SEALED CERAMIC SURFACE MOUNT PACKAGE FOR HIGH RELIABILITY APPLICATIONS 1 2 Seme LAB
2N4392CSMSMALL SIGNAL N.CHANNEL J.FET IN A HERMETICALLY SEALED CERAMIC SURFACE MOUNT PACKAGE FOR HIGH RELIABILITY APPLICATIONS 1 2 Seme LAB

Link URL

Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Bookmark   |   Link Exchange   |   Manufacturer List
All Rights ReservedĀ© Alldatasheet.com 2003 - 2017    


Mirror Sites
English : Alldatasheet.com  , Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp  |   Russian : Alldatasheetru.com
Korean : Alldatasheet.co.kr   |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com  |   Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl