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HI5634 Datasheet(PDF) 1 Page - Intersil Corporation

Part No. HI5634
Description  High Performance Programmable Phase-Locked Loop for LCD Applications
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Maker  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
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 1 page
background image
1
File Number
4745
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
| Copyright
© Intersil Corporation 1999
I2C Bus is a Trademark of Philips Corporation.
PRELIMINARY
HI5634
High Performance Programmable
Phase-Locked Loop for LCD Applications
The HI5634 is a low cost but very high-performance
frequency generator for line-locked and genlocked high
resolution video applications. Utilizing an advanced low
voltage CMOS mixed signal technology, the HI5634 is an
effective clock solution for video projectors and displays at
resolutions from VGA to beyond UXGA
The HI5634 offers pixel clock outputs in both differential (to
250MHz) and single-ended (to 150MHz) formats. Digital
phase adjustment circuitry allows user control of the pixel
clock phase relative to the recovered sync signal. A second
differential output at half the pixel clock rate enables
deMUXing of multiplexed A/D converters. The FUNC pin
provides either the regenerated input from the phase-locked
loop (PLL) divider chain output or a re-synchronized and
sharpened input HSYNC.
The advanced PLL utilizes either its internal programmable
feedback divider or an external divider. The device is
programmed by a standard I2C-bus® serial interface.
Simplified Block Diagram
Features
• Pixel Clock Frequencies up to 250MHz
• Very Low Jitter
• Digital Phase Adjustment (DPA) for Clock Outputs
• Balanced PECL Differential Outputs
• Single-Ended SSTL_3 Clock Outputs
• Double-Buffered PLL/DPA Control Registers
• Independent Software Reset for PLL/DPA
• External or Internal Loop Filter Selection
• Uses 3.3V Supply. Inputs are 5V Tolerant.
•I2C-bus Serial Interface can Run at Either Low Speed
(100kHz) or High Speed (400kHz)
• Lock Detection
Applications
• LCD Monitors and Video Projectors
• Genlocking Multiple Video Subsystems
• Frequency Synthesis
Pinout
HI5634
(SOIC)
TOP VIEW
Ordering Information
PART NUMBER
TEMP.
RANGE (oC)
PACKAGE
PKG.
NO.
HI5634CB
0 to 70
24 Ld SOIC
M24.3
PHASE
LOCKED
LOOP
DIGITAL
ADJUST
CLK
CLK/2
FUNC
LOOP FILTER
OSC
HSYNC
I2C INTERFACE
PHASE
VDDD
VSSD
SDA
SCL
1
2
3
4
24
23
22
21
IREF
CLK/2+ (PECL)
CLK/2- (PECL)
CLK+ (PECL)
PDEN
EXTFB
HSYNC
EXTFIL
5
6
7
8
20
19
18
17
CLK- (PECL)
VSSQ
VDDQ
CLK (SSTL)
EXTFILRET
VDDA
VSSA
OSC
9
10
11
12
16
15
14
13
CLK/2 (SSTL)
FUNC (SSTL)
LOCK/REF (SSTL)
I2CADR
Data Sheet
May 1999




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