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HI5634 Datasheet(PDF) 2 Page - Intersil Corporation

Part No. HI5634
Description  High Performance Programmable Phase-Locked Loop for LCD Applications
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Maker  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
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 2 page
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2
Pin Descriptions
PIN NO.
PIN NAME
TYPE
DESCRIPTION
COMMENTS
1
VDDD
PWR
Digital Supply
3.3V to Digital Sections
2
VSSD
PWR
Digital Ground
3
SDA
IN/OUT
Serial Data
I2C-Bus (Note 1)
4
SCL
IN
Serial Clock
I2C-Bus (Note 1)
5
PDEN
IN
PFD Enable
Suspends Charge Pump (Note1)
6
EXTFB
IN
External Feedback In
External Divider Input to PFD (Note1)
7
HSYNC
IN
Horizontal Sync
Clock Input to PLL (Note1)
8
EXTFIL
IN
External Filter
External PLL Loop Filter
9
EXTFILRET
IN
External Filter Return
External PLL Loop Filter Return
10
VDDA
PWR
Analog Supply
3.3V for Analog Circuitry
11
VSSA
PWR
Analog Ground
Ground for Analog Circuitry
12
OSC
IN
Oscillator
Input From Crystal Oscillator Package (Notes 1, 2)
13
I2CADR
IN
I2C Address
Chip I2C Address Select
Low = 4Dh Read, 4Ch Write
High = 4Fh Read, 4Eh Write
14
LOCK/REF (SSTL)
OUT
Lock Indicator/Reference
Displays PLL or DPA Lock or REF Input
15
FUNC (SSTL)
OUT
Function Output
SSTL_3 Selectable HSYNC Output
16
CLK/2 (SSTL)
OUT
Pixel Clock/2 Out
SSTL_3 Driver to ADC DeMUX Input
17
CLK (SSTL)
OUT
Pixel Clock Out
SSTL_3 Driver to ADC
18
VDDQ
PWR
Output Driver Supply
3.3V to Output Drivers
19
VSSQ
PWR
Output Driver Ground
Ground for Output Drivers
20
CLK- (PECL)
OUT
Pixel Clock Out
Inverted PECL Driver to ADC. Open Drain Output.
21
CLK+ (PECL)
OUT
Pixel Clock Out
PECL Driver to ADC. Open Drain Output.
22
CLK/2- (PECL)
OUT
Pixel Clock/2 Out
Inverted PECL Driver to ADC DeMUX Input. Open Drain
Output.
23
CLK/2+ (PECL)
OUT
Pixel Clock/2 Out
PECL Driver to ADC DeMUX Input. Open Drain Output.
24
IREF
IN
Reference Current
Reference Current for PECL Outputs
NOTES:
1. These LVTTL inputs are 5V tolerant.
2. Connect to ground if unused.
HI5634




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