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HI5731BIB Datasheet(PDF) 8 Page - Intersil Corporation |
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HI5731BIB Datasheet(HTML) 8 Page - Intersil Corporation |
8 / 15 page 3-8 FIGURE 18. SPURIOUS FREE DYNAMIC RANGE = 71.16dBc FIGURE 19. SPURIOUS FREE DYNAMIC RANGE = 70.5dBc FIGURE 20. SPURIOUS FREE DYNAMIC RANGE = 70dBc Pin Descriptions PIN NUMBER PIN NAME PIN DESCRIPTION 1-12 D11 (MSB) thru D0 (LSB) Digital Data Bit 11, the Most Significant Bit thru Digital Data Bit 0, the Least Significant Bit. 15 CLK Data Clock Pin DC to 100 MSPS. 13, 14 NC No Connect. 16 DVCC Digital Logic Supply +5V. 17, 28 DGND Digital Ground. 18 DVEE -5.2V Logic supply. 23 RSET External resistor to set the full scale output current. IFS = 16 x (VREF OUT / RSET). Typically 976Ω. 27 AGND Analog Ground supply current return pin. 19 ARTN Analog Signal Return for the R/2R ladder. 21 IOUT Current Output Pin. 20 IOUT Complementary Current Output Pin. 22 AVEE -5.2V Analog Supply. 24 CTRL IN Input to the current source base rail. Typically connected to CTRL OUT and a 0.1 µF capacitor to AVEE. Allows external control of the current sources. 25 CTRL OUT Control Amplifier Out. Provides precision control of the current sources when connected to CTRL IN such that IFS = 16 x (VREF OUT / RSET). 26 REF OUT -1.23V (Typ) bandgap reference voltage output. Can sink up to 125 µA or be overdriven by an external reference capable of delivering up to 2mA. Typical Performance Curves (Continued) ∆MKR -71.16dB 2.99MHz 10dB/ ATTEN 20dB RL -10.0dBm C S STOP FREQUENCY 20MHz START FREQUENCY 500kHz fC = 40 MSPS fO = 2.02MHz ∆MKR -70.50dB 1.98MHz 10dB/ ATTEN 20dB RL -10.0dBm STOP FREQUENCY 40MHz START FREQUENCY 500kHz C S fC = 80 MSPS fO = 2.02MHz ∆MKR -70.00dB 4.13MHz 10dB/ ATTEN 20dB RL -10.0dBm C S STOP FREQUENCY 50MHz START FREQUENCY 500kHz fC = 100 MSPS fO = 2.02MHz HI5731 |
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