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HI5812JIP Datasheet(PDF) 9 Page - Intersil Corporation |
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HI5812JIP Datasheet(HTML) 9 Page - Intersil Corporation |
9 / 13 page 6-1797 Theory of Operation HI5812 is a CMOS 12-Bit Analog-to-Digital Converter that uses capacitor-charge balancing to successively approximate the analog input. A binarily weighted capacitor network forms the A/D heart of the device. See the block diagram for the HI5812. The capacitor network has a common node which is connected to a comparator. The second terminal of each capacitor is individually switchable to the input, VREF+ or VREF-. During the first three clock periods of a conversion cycle, the switchable end of every capacitor is connected to the input and the comparator is being auto-balanced at the capacitor common node. During the fourth period, all capacitors are disconnected from the input; the one representing the MSB (D11) is connected to the VREF+ terminal; and the remaining capacitors to VREF-. The capacitor-common node, after the charges balance out, will indicate whether the input was above 1/2 of (VREF+ - VREF-). At the end of the fourth period, the comparator output is stored and the MSB capacitor is either left connected to VREF+ (if the comparator was high) or returned to VREF-. This allows the next comparison to be at either 3/4 or 1/ 4 of (VREF+ - VREF -). At the end of periods 5 through 14, capacitors representing D10 through D1 are tested, the result stored, and each capacitor either left at VREF+ or at VREF-. At the end of the 15th period, when the LSB (D0) capacitor is tested, (D0) and all the previous results are shifted to the output registers and drivers. The capacitors are reconnected to the input, the comparator returns to the balance state, and the data-ready output goes active. The conversion cycle is now complete. Analog Input The analog input pin is a predominately capacitive load that changes between the track and hold periods of the conversion cycle. During hold, clock period 4 through 15, the input loading is leakage and stray capacitance, typically less than 5 µA and 20pF. At the start of input tracking, clock period 1, some charge is dumped back to the input pin. The input source must have low enough impedance to dissipate the current spike by the end of the tracking period as shown in Figure 18. The amount of charge is dependent on supply and input voltages. The average current is also proportional to clock frequency. TABLE 1. PIN DESCRIPTIONS PIN NO. NAME DESCRIPTION 1 DRDY Output flag signifying new data is available. Goes high at end of clock period 15. Goes low when new conversion is started. 2 D0 Bit 0 (Least Significant Bit, LSB). 3 D1 Bit 1. 4 D2 Bit 2. 5 D3 Bit 3. 6 D4 Bit 4. 7 D5 Bit 5. 8 D6 Bit 6. 9 D7 Bit 7. 10 D8 Bit 8. 11 D9 Bit 9. 12 VSS Digital Ground (0V). 13 D10 Bit 10. 14 D11 Bit 11 (Most Significant Bit, MSB). 15 OEM Three-State Enable for D4-D11. Active low input. 16 VAA- Analog Ground, (0V). 17 VAA+ Analog Positive Supply. (+5V) (See text.) 18 VIN Analog Input. 19 VREF+ Reference Voltage Positive Input, sets 4095 code end of input range. 20 VREF- Reference Voltage Negative Input, sets 0 code end of input range. 21 STRT Start Conversion Input Active Low, recognized after end of clock period 15. 22 CLK CLK Input or Output. Conversion functions are synchronized to positive going edge. (See text.) 23 OEL Three-State Enable for D0 D3. Active Low Input. 24 VDD Digital Positive Supply (+5V). 20mA 10mA 0mA 5V 0V 5V 0V IIN CLK DRDY 200ns/DIV. CONDITIONS: VDD = VAA+ = 5.0V, VREF+ = 4.608V, VIN = 4.608V, CLK = 750kHz, TA = 25 oC FIGURE 18. TYPICAL ANALOG INPUT CURRENT HI5812 |
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