6-1798

As long as these current spikes settle completely by end of

the signal acquisition period, converter accuracy will be

preserved. The analog input is tracked for 3 clock cycles.

With an external clock of 750kHz the track period is 4

µs.

A simplified analog input model is presented in Figure 19.

380pF capacitor being charged through a 420

Ω internal

switch resistance. The time constant is 160ns. To charge this

capacitor from an external “zero

Ω” source to 0.5 LSB

(1/8192), the charging time must be at least 9 time constants

or 1.4

for a 4

µs acquisition time settling to within 0.5LSB is 750Ω.

If the clock frequency was slower, or the converter was not

restarted immediately (causing a longer sample time), a

higher source impedance could be tolerated.

Reference Input

impedance source and be well decoupled.

As shown in Figure 20, current spikes are generated on the

reference pin during each bit test of the successive approxi-

mation part of the conversion cycle as the charge-balancing

periods 5 - 14). These current spikes must settle completely

during each bit test of the conversion to not degrade the

biased for nulling the converters offset it must be stable

during the conversion cycle.

The HI5812 is specified with a 4.608V reference, however, it

will operate with a reference down to 3V having a slight

degradation in performance. A typical graph of accuracy vs

reference voltage is presented.

Full Scale and Offset Adjustment

In many applications the accuracy of the HI5812 would be

sufficient without any adjustments. In applications where

accuracy is of utmost importance full scale and offset errors

may be adjusted to zero.

analog input range and may be used for offset and full scale

returned to a clean ground, and the offset adjustment done

must be well decoupled.

Full scale and offset error can also be adjusted to zero in the

Control Signal

The HI5812 may be synchronized from an external source

by using the STRT (Start Conversion) input to initiate conver-

sion, or if STRT is tied low, may be allowed to free run. Each

conversion cycle takes 15 clock periods.

The input is tracked from clock period 1 through period 3,

then disconnected as the successive approximation takes

data), the output is updated.

The DRDY (Data Ready) status output goes high (specified

The 12 data bits are available in parallel on three-state bus

driver outputs. When low, the OEM input enables the most

significant byte (D4 through D11) while the OEL input

specify the output enable and disable times.

If the output data is to be latched externally, either the trailing

edge of data ready or the next falling edge of the clock after

data ready goes high can be used.

When STRT input is used to initiate conversions, operation is

slightly different depending on whether an internal or

external clock is used.

Figure 3 illustrates operation with an internal clock. If the

period 1, and is not reapplied during that period, the clock

will shut off after entering period 2. The input will continue to

track and the DRDY output will remain high during this time.

now initiate a new conversion. The STRT signal (after a

Depending on how long the clock was shut off, the low

portion of clock period 2 may be longer than during the

remaining cycles.

R

SOURCE(MAX)

t

AC Q

–

C

N1

+

()

–

[]

--------------------------------------------------------------

R

SW

–

=

FIGURE 19. ANALOG INPUT MODEL IN TRACK MODE

20mA

10mA

0mA

5V

0V

5V

0V

CLK

DRDY

2

µs/DIV.

FIGURE 20. TYPICAL REFERENCE INPUT CURRENT

HI5812