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HI7131 Datasheet(PDF) 11 Page - Intersil Corporation |
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HI7131 Datasheet(HTML) 11 Page - Intersil Corporation |
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11 / 21 page  3-1836 Analog Section Description Figure 5A shows a simplified diagram of the analog section of the HI7131 and HI7133. The circuit performs basic phases of dual slope integration. Furthermore, the device incorporates 2 additional phases called “Auto-Zero” and “Zero Integrate”. The device accepts differential input signals and reference voltages. Also, there is a reference voltage generator which sets the COMMON pin 2.8V below the V+ supply. A complete conversion cycle is divided into the following four phases: 1. Auto-Zero (A/Z) 2. Signal Integrate (INT) 3. Deintegrate or Reference Integrate (DE ±) 4. Zero Integrate (ZI) Digitally controlled analog switches direct the appropriate signals for each phase of the conversion. Auto-Zero Phase During auto-zero three things occur. First, IN HI is discon- nected from the device internal circuitry and internally shorted to IN LO. Second, the reference capacitor is charged to the reference voltage. Third, a feedback loop is closed around the system to charge the auto-zero capacitor CAZ and integrating capacitor CINT to compensate for offset voltages in the buffer amplifier, integrator, and comparator. Since the comparator is included in the loop, the A/Z accu- racy is limited only by the noise of the system. In any case, the offset referred to the input is less than 10 µV. Signal Integrate Phase During signal integrate the auto-zero loop is opened and the internal INPUT HIGH is connected to the external pins. The converter then integrates the differential voltage between IN HI and IN LO for a fixed time. This differential voltage can be within a wide input common mode range: up to 1V from either supply. At the end of this phase, the polarity of the integrated signal is determined. Deintegrate Phase During this phase the IN LO and the internal INPUT HIGH are connected across the previously charged reference capacitor. The bridge type circuitry within the chip ensures that the capacitor will be connected with the correct polarity to cause the integrator output to return to zero. The time required for the output to return to zero is proportional to the input signal. As specified before, the digital reading displayed is: . Zero Integrate Phase This phase is provided to eliminate overrange hangover and causes fast recovery from heavy overrange. During this phase a feedback loop is closed around the system by connecting comparator output to internal INPUT HIGH. This will discharge the integrator capacitor (CINT), causing the integrator output return to zero. During this phase the refer- ence capacitor is also connected to reference input, charg- ing to the reference voltage. A typical integrator output voltage during different phases is shown on the “Design Information Summary Sheet.” This integrator output is for negative inputs and is referred to IN LO. For positive inputs the integrator output will go negative. Digital Section Description Figure 6 shows the block diagram of the digital section of the HI7131. The diagram shows the clock generator, control logic, counters, latches and display decoder drivers. An internal digital ground is generated from a 6V Zener diode and a large P-Channel source follower. This supply is capa- ble of absorbing the relatively large capacitive currents when the LCD backplane (BP) and segment drivers are switched. Display Drivers A typical segment output driver consists of P-Channel and N-Channel MOSFETs. An LCD consists of a backplane (BP) and segments. BP covers the whole area under the segments. Because of the nature of the LCDs, they should be driven by square waves. The BP frequency is the clock frequency divided by 800. For three readings/second this is a 60Hz square-wave with a nominal amplitude of 5V. The segments are driven at the same frequency and amplitude and are in phase with BP when OFF, but out of phase when ON. In all cases negligible DC voltage exists across the segments. The polarity indica- tion is “ON” for negative analog inputs. If IN LO and IN HI are reversed, this indication can be reversed also, if desired. The HI7131 is a direct display drive (versus multiplexed) and each segment in each digit has its own segment driver. The display font and the segment assignment on the display are also shown in Figure 6. Figure 6 shows the block diagram of the digital section of the HI7133. The diagram shows the clock generator, control logic, counters, latches and display decoder drivers. The supply rails of the digital circuitry are V+ and GND. Display Drivers A typical segment output consists of a P-Channel and an N-Channel MOSFET. This configuration is designed to drive common anode LED displays. The nominal sink current for each segment is 8mA, a typical value for instrument size common anode LED displays. The driver for the thousand digit is twice as big as other segments and can sink 16mA since it is actually driving 2 segments. The sink current for the polarity driver is 7mA. The polarity driver is on for negative inputs. The HI7133 is a direct display drive (versus multiplexed) and each segment in each digit has its own seg- ment driver. The display font and the segment assignment on the display are also shown in Figure 7. Clock Generator The clock generator circuit basically includes 2 CMOS inverters and a divide-by-4 counter. It is designed to be used in 2 different basic configurations. DIGITA L READING 1000 V INHI V INLO – V REFHI V REFLO – -------------------------------------------------- = HI7131, HI7133 |
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