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HI5960SOICEVAL1 Datasheet(PDF) 3 Page - Intersil Corporation |
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HI5960SOICEVAL1 Datasheet(HTML) 3 Page - Intersil Corporation |
3 / 12 page 3 Pin Descriptions PIN NO. PIN NAME DESCRIPTION 1-14 D13 (MSB) Through D0 (LSB) Digital Data Bit 13, (Most Significant Bit) through Digital Data Bit 0, (Least Significant Bit). 15 SLEEP Control Pin for Power-Down mode. Sleep Mode is active high; Connect to ground for Normal Mode. Sleep pin has internal 20 µA active pulldown current. 16 REFLO Connect to analog ground to enable internal 1.2V reference or connect to AVDD to disable internal reference. 17 REFIO Reference voltage input if internal reference is disabled. Reference voltage output if internal reference is enabled. Use 0. 1µF cap to ground when internal reference is enabled. 18 FSADJ Full Scale Current Adjust. Use a resistor to ground to adjust full scale output current. Full Scale Output Current = 32 x VFSADJ/RSET. 19 COMP1 For use in reducing bandwidth/noise. Recommended: connect 0.1 µF to AVDD. 21 IOUTB The complimentary current output of the device. Full scale output current is achieved when all input bits are set to binary 0. 22 IOUTA Current output of the device. Full scale output current is achieved when all input bits are set to binary 1. 23 COMP2 Connect 0.1 µF capacitor to ACOM. 24 AVDD Analog Supply (+3V to +5V). 20, 25 ACOM Connect to Analog Ground. 26 DCOM Connect to Digital Ground. 27 DVDD Digital Supply (+3V to +5V). 28 CLK Clock Input. Input data to the DAC passes through the “master” latches when the clock is low and is latched into the “master” latches when the clock is high. Data presented to the “slave” latch passes through when the clock is logic high and is latched into the “slave” latches when the clock is logic low. Adequate setup time must be allowed for the MSBs to pass through the thermometer decoder before the clock goes high. This master-slave arrangement comprises an edge-triggered flip-flop, with the DAC being updated on the rising clock edge. It is recommended that the clock edge be skewed such that setup time is larger than the hold time. HI5960 |
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