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HI7191IP Datasheet(PDF) 10 Page - Intersil Corporation |
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HI7191IP Datasheet(HTML) 10 Page - Intersil Corporation |
10 / 24 page 1906 Analog Inputs The analog input on the HI7191 is a fully differential input with programmable gain capabilities. The input accepts both unipolar and bipolar input signals and gains range from 1 to 128. The common mode range of this input is from AVSS to AVDD provided that the absolute value of the analog input voltage lies within the power supplies. The input impedance of the HI7191 is dependent upon the modulator input sam- pling rate and the sampling rate varies with the selected PGIA gain. Table 3 below shows the sampling rates and input impedances for the different gain settings of the HI7191. Note that this table is valid only for a 10MHz master clock. If the input clock frequency is changed then the input impedance will change accordingly. The equation used to calculate the input impedance is: where Cin is the nominal input capacitance (8pF) and fS is the modulator sampling rate. Bipolar/Unipolar Input Ranges The input on the HI7191 can accept either unipolar or bipolar input voltages. Bipolar or unipolar options are chosen by pro- gramming the B/U bit of the Control Register. Programming the part for either unipolar or bipolar operation does not change the input signal conditioning. The inputs are differential, and as a result are referenced to the voltage on the VINLO input. For example, if VINLO is +1.25V and the HI7191 is configured for unipolar operation with a gain of 1 and a VREF of +2.5V, the input voltage range on the VINLO input is +1.25V to +3.75V. If VINLO is +1.25V and the HI7191 is configured for bipolar mode with gain of 1 and a VREF of +2.5V, the analog input range on the VINHI input is -1.25V to +3.75V. Programmable Gain Instrumentation Amplifier The Programmable Gain Instrumentation Amplifier allows the user to directly interface low level sensors and bridges directly to the HI7191. The PGIA has 4 selectable gain options of 1, 2, 4, 8 which are implemented by multiple sampling of the input signal. Input signals can be gained up further to 16, 32, 64 or 128. These higher gains are implemented in the digital section of the design to maintain a high signal to noise ratio through the front end amplifiers. The gain is digitally programmable in the Control Register via the serial interface. For optimum PGIA performance the VCM pin should be tied to the mid point of the analog supplies. Differential Reference Input The reference inputs of the of the HI7191, VRHI and VRLO, provide a differential reference input capability. The nominal differential voltage (VREF = VRHI - VRLO) is +2.5V and the common mode voltage cab be anywhere between AVSS and AVDD. Larger values of VREF can be used without degradation in performance with the maximum reference voltage being VREF = +5V. Smaller values of VREF can also be used but performance will be degraded since the LSB size is reduced. The full scale range of the HI7191 is defined as: and VRHI must always be greater than VRLO for proper operation of the device. The reference inputs provide a high impedance dynamic load similar to the analog inputs and the effective input impedance for the reference inputs can be calculated in the same manner as it is for the analog input impedance. The only difference in the calculation is that CIN for the reference inputs is 10.67pF. Therefor, the input impedance range for the reference inputs is from 149k Ω in a gain of 8 or higher mode to 833k Ω in the gain of 1 mode. VCM Input The voltage at the VCM input is the voltage that the internal analog circuitry is referenced to and should always be tied to the midpoint of the AVDD and AVSS supplies. This point provides a common mode input voltage for the internal oper- ational amplifiers and must be driven from a low noise, low impedance source if it is not tied to analog ground. Failure to do so will result in degraded HI7191 performance. It is recommended that VCM be tied to analog ground when operating off of AVDD = +5V and AVSS = -5V supplies. VCM also determines the headroom at the upper and lower ends of the power supplies which is limited by the common mode input range where the internal operational amplifiers remain in the linear, high gain region of operation. The HI7191 is designed to have a range of AVSS +1.8V < VCM < AVDD - 1.8V. Exceeding this range on the VCM pin will compromise the device performance. Transducer Burn-Out Current Source The VINHI input of the HI7191 contains a 500nA (Typ) current source which can be turned on/off via the Control Register. This current source can be used in checking whether a trans- ducer has burnt-out or become open before attempting to take measurements on that channel. When the current source is turned on an additional offset will be created indicating the presence of a transducer. The current source is controlled by the BO bit (Bit 4) in the Control Register and is disabled on power up. See Figure 8 for an applications circuit. TABLE 3. EFFECTIVE INPUT IMPEDANCE vs GAIN GAIN SAMPLING RATE (kHz) INPUT IMPEDANCE (M Ω) 1 78.125 1.6 2 156.25 0.8 4 312.5 0.4 8, 16, 32, 64, 128 625 0.2 ZIN = 1/(CIN x fS), FSRBIPOLAR = 2 x VREF/GAIN FSRUNIPOLAR = VREF/GAIN HI7191 |
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