Electronic Components Datasheet Search |
|
FN4819.1 Datasheet(PDF) 4 Page - Intersil Corporation |
|
FN4819.1 Datasheet(HTML) 4 Page - Intersil Corporation |
4 / 8 page 4 Functional Pin Description UGATE (Pin 1) Upper gate drive output. Connect to gate of high-side power N-Channel MOSFET. BOOT (Pin 2) Floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor between this pin and the PHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See the Internal Bootstrap Device section under DESCRIPTION for guidance in choosing the appropriate capacitor value. PWM (Pin 3) The PWM signal is the control input for the driver. The PWM signal can enter three distinct states during operation, see the three-state PWM Input section under DESCRIPTION for further details. Connect this pin to the PWM output of the controller. GND (Pin 4) Bias and reference ground. All signals are referenced to this node. LGATE (Pin 5) Lower gate drive output. Connect to gate of the low-side power N-Channel MOSFET. VCC (Pin 6) Connect this pin to a +12V bias supply. Place a high quality bypass capacitor from this pin to GND. PVCC (Pin 7) For the HIP6601, this pin supplies the upper gate drive bias. Connect this pin from +12V down to +5V. For the HIP6603, this pin supplies both the upper and lower gate drive bias. Connect this pin to either +12V or +5V. PHASE (Pin 8) Connect this pin to the source of the upper MOSFET and the drain of the lower MOSFET. The PHASE voltage is monitored for adaptive shoot-through protection. This pin also provides a return path for the upper gate drive. Description Operation Designed for versatility and speed, the HIP6601 and HIP6603 dual MOSFET drivers control both high-side and low-side N- Channel FETs from one externally provided PWM signal. The upper and lower gates are held low until the driver is initialized. Once the VCC voltage surpasses the VCC Rising Threshold (See Electrical Specifications), the PWM signal takes control of gate transitions. A rising edge on PWM initiates the turn-off of the lower MOSFET (see Timing Diagram). After a short propagation delay [TPDLLGATE], the lower gate begins to fall. Typical fall times [TFLGATE] are provided in the Electrical Specifications section. Adaptive shoot-through circuitry monitors the LGATE voltage and determines the upper gate delay time [TPDHUGATE] based on how quickly the LGATE voltage drops below 1.0V. This prevents both the lower and upper MOSFETs from conducting simultaneously or shoot-through. Once this delay period is complete the upper gate drive begins to rise [TRUGATE] and the upper MOSFET turns on. Timing Diagram PWM UGATE LGATE TPDLLGATE TFLGATE TPDHUGATE TRUGATE TPDLUGATE TFUGATE TPDHLGATE TRLGATE HIP6601, HIP6603 |
Similar Part No. - FN4819.1 |
|
Similar Description - FN4819.1 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |