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HIP7030A2 Datasheet(PDF) 11 Page - Intersil Corporation |
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HIP7030A2 Datasheet(HTML) 11 Page - Intersil Corporation |
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11 / 56 page  11 All Port D I/Os are configured as inputs during a POR, COP, or external reset. Refer to PD0-PD4 Special Function I/O Lines under Port A and D I/O Lines for a detailed description of programming the Port D I/O lines. VPWOUT (Variable Pulse Width Out - Output), VPWIN (Variable Pulse Width In - Input) These two lines are used to interface to the J1850 bus trans- ceiver. VPWOUT is the pulse width modulated output of the SEN- DEC encoder block. VPWIN is the inverted input to the SENDEC decoder block. See VPW Symbol Encoder/Decoder (SENDEC) for a detailed description of the J1850 interface pins. MISO (Master-in/Slave-out - Input/Output), MOSI (Master-out/Slave-in - Input/Output), SCK (Serial Clock - Input/Output), SS (Slave Select - Input) These four lines constitute the Serial Peripheral Interface (SPI) communications port. The MCU can be configured as a SPI “master” or as a SPI “slave”. In master mode MOSI and SCK function as outputs and MISO functions as an input. In slave mode MOSI and SCK are inputs and MISO is an output. SS is always an input. Serial data words are transmitted and received over the MISO/MOSI lines synchronously with the SCK clock stream. The word size is fixed at 8-bits. Single buffering is used which results in an inherent inter-byte delay. The master device always provides the synchronizing clock. A low on the SS line causes the MCU to immediately assume the role of slave, regardless of it’s current mode. This allows multi-master systems to be constructed with appropriate arbitration protocols. See the detailed discussion of the SPI interface under Serial Peripheral Interface (SPI). Integrated Hardware I/O Functions PORT A Each of the Parallel Port pins of Port A may be individually programmed as an input or an output under software control. The direction of each pin is determined by the state of the corresponding bit in the Port A Data Direction Register (DDRA, location $04). Any Port A pin is configured as an output if its corresponding DDR bit is set to a logic one. A pin is configured as an input if its corresponding DDR bit is cleared to a logic zero. Any reset will clear all DDR bits, which configures all Port A and D pins as inputs. The data direction register is capable of being written to or read by the processor. Refer to Figure 5 and Table 1. Port A is an 8-bit wide read-write data register. Regardless of the state of the DDRA bits, all Port A data latches are modified with each write to Port A. When Port A is read, the value read for bits programmed as outputs, is the contents of the data latch, not the pin. The value read for bits pro- grammed as inputs is the value on the pin. PD0-PD4 SPECIAL FUNCTION I/O LINES These five lines comprise Port D. The five lines can be indi- vidually programmed to provide input or output capabilities similar to the eight Port A lines. Additionally, each of the lines FIGURE 5A. PORT A I/O PAD CIRCUITRY PAD PORT DATA PORT DRR INTERNAL LOGIC VDD P N FIGURE 5B. PORT A FUNCTIONAL BLOCK DIAGRAM 76543210 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 PORT A DATA DIRECTION REGISTER (DDRA, LOCATION $04) 76543210 A7 A6 A5 A4 A3 A2 A1 A0 PORT A DATA REGISTER (PORTA, LOCATION $00) TABLE 1. PORT A TRUTH TABLE (NOTE 1) R/W DDR I/O PIN FUNCTION W 0 The I/O pin is in input mode. Data is written into the output data latch W 1 Data is written into the output data latch and simultaneously output to the I/O pin. R 0 The state of the I/O pin is read. R 1 The I/O pin is in output mode. The output data latch is read. NOTE: 1. R/W is an internal signal which equals R when reading the Port Data Register and equals W when writing the Port Data Register. DATA DIR REG BIT LATCHED OUTPUT DATA BIT INPUT REG BIT INPUT I/O OUTPUT I/O PIN HIP7030A2 |
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