HIP7030A2P datasheet(2/56 Pages) INTERSIL

Part #	HIP7030A2P

Description	J1850 8-Bit 68HC05 Microcontroller

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Manufacturer	INTERSIL [Intersil Corporation]

Direct Link	http://www.intersil.com/cda/home

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2

Block Diagram

Pinout

HIP7030A2

(PDIP, SOIC)

TOP VIEW

VPW SYMBOL

ENCODER /

DECODER AND

ARBITRATION

SPI

SYSTEM

CPU

CONTROL

CPU

ALU

INDEX

REGISTER

CONDITION CODE

REGISTER

STACK

POINTER

PROGRAM

COUNTER HIGH

PROGRAM

COUNTER LOW

ACCUMULATOR

WATCHDOG AND

SLOW CLOCK DETECT

176 x 8

STATIC RAM

2110 x 8

ROM

242 x 8

BUILT-IN-TEST

ROM

OSCILLATOR

AND

÷ 2

TIMER SYSTEM

PORT D

DIR

REG

PORT D

SFR

REG

PORT

A

REG

DATA

DIR

REG

PORT D

REG

INTERNAL

PROCESSOR

CLOCK

INTERNAL PROCESSOR

CLOCK

SYMBOL INT

OSCB

5

6

RESET

IRQ

VPW OUT

VPW IN

SCK

MOSI

MISO

SS

4

3

25

26

27

28

16

23

24

8

5

6

5

8

A

X

CC

S

PCH

PCL

1

2

15

14

13

12

11

10

9

8

21

20

19

18

17

TCAP

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

PD0

PD1

PD2, V2

PD3, V3

PD4, VR

VSS 22

VDD

7

TCMP

OSCIN

OSCOUT

+

-

+

-

TCAP

TCMP

VPW IN

VPW OUT

RESET

IRQ

VDD

PA7

PA6

PA5

PA4

PA3

PA2

PA1

SS

MOSI

SCK

OSCIN

OSCOUT

PD0

PD2, V2

PD3, V3

PD4, VREF

OSCB

PA0

MISO

VSS

PD1

28

27

26

25

24

23

22

21

20

19

18

17

16

15

1

2

3

4

5

6

7

8

9

10

11

12

13

14

HIP7030A2

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HIP7030A2P Datasheet(PDF) 2 Page - Intersil Corporation

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