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HIP9010AB Datasheet(PDF) 11 Page - Intersil Corporation |
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HIP9010AB Datasheet(HTML) 11 Page - Intersil Corporation |
11 / 12 page 4-11 Test Multiplexer This circuit receives the positive and negative outputs out of the two integrators, together with the outputs from different parts of the chip. The output is controlled by the fifth programming word of the communications protocol. This multiplexes the switch capacitor filter output, the gain control output as well as the antialias output. Differential to Single-ended Converter This signal takes the output of the two integrators (through the test multiplexer circuit) and provides a signal that is the sum of the two signals. This technique is used to improve the noise immunity of the system. Output Buffer This output amplifier is the same as the input amplifier used to interface to the sensors. For test purposes when we look at the output of the antialias filter, the input amplifiers are in the power down mode. TABLE 4. INTERGRATE/HOLD TIMING REQUIREMENTS DESCRIPTION UNITS T1 maximum rise time of the INT/HOLD signal. 45ns T2 maximum time after INT/HOLD rises for the INOUT to begin to intergrate. 20 µs T3 maximum fall time of INT/HOLD signal. 45ns T4 typical time after INT/HOLD goes low before chip goes into hold state. 20 µs T5 minimum INT/HOLD time during power up sequence. 1 µs CS INT/HOLD FIGURE 7. POWER UP SEQUENCE INT/HOLD INTOUT T1 T2 T3 T4 FIGURE 8. INTEGRATOR TIMING HIP9010 |
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