6-5

Timing Waveforms

NOTE:

1. W is high for entire cycle and D is ignored. Address is stable by the time E goes low and remains valid until E goes high.

FIGURE 1. READ CYCLE 1: CONTROLLED BY E

NOTE:

1. W is high for the entire cycle and D is ignored. E is stable prior to A becoming valid and after A becomes invalid.

FIGURE 2. READ CYCLE 2: CONTROLLED BY ADDRESS

NOTE:

1. In this mode, E rises after W. The address must remain stable whenever both E and W are low.

FIGURE 3. WRITE CYCLE 1: CONTROLLED BY W (LATE WRITE)

(4) TELQX

A

(3) TELQV

(5) TEHQX

(7) TEHQZ

E

Q

(1) TAVAX

(2) TAVQV

(4) TELQX

A

E

Q

(7) TEHQZ

(6) TAXQX

A

(17) TAVWH

(9) TELWH

(12) TWHAX

(10) TWLWH

(11)

(7) TEHQZ

(14) TWHDX

(13) TDVWH

(15) TWLQZ

(4)

TELQX

(16) TWHQX

(8) TAVAX

E

W

D

Q

TAVWL

HM-65262