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HMP8156 Datasheet(PDF) 7 Page - Intersil Corporation |
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HMP8156 Datasheet(HTML) 7 Page - Intersil Corporation |
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7 / 33 page  7 16-Bit YCbCr, 16-Bit RGB, 24-Bit RGB Formats without 2X Upscaling When 16-bit YCbCr, 16-bit RGB data, or 24-bit RGB format is selected without 2X upscaling, the pixel data is latched on the rising edge of CLK2 while CLK is low. Overlay data is also latched on the rising edge of CLK2 while CLK is low. The pixel and overlay input timing is shown in Figures 3 - 5. As inputs, BLANK, HSYNC, and VSYNC are latched on the rising edge of CLK2 while CLK is low. As outputs, HSYNC, VSYNC, and BLANK are output following the rising edge of CLK2 while CLK is high. In these modes of operation, CLK is one-half the CLK2 frequency. 16-Bit YCbCr, 16-Bit RGB, 24-Bit RGB Formats with 2X Upscaling When 16-bit YCbCr, 16-bit RGB data, or 24-bit RGB format is selected and 2X upscaling is enabled, data is latched on the rising edge of CLK2 while CLK is low. Overlay data is latched on the rising edge of CLK2 while CLK is low. The pixel and overlay input timing is shown in Figures 6-8 As inputs, BLANK, HSYNC, and VSYNC are latched on the rising edge of CLK2 while CLK is low. As outputs, HSYNC, VSYNC, and BLANK are output following the rising edge of CLK2 while CLK is high. CLK is one-fourth the CLK2 fre- quency. FIGURE 2. PIXEL AND OVERLAY INPUT TIMING - 8-BIT YCBCR WITH 2X UPSCALING CLK CLK2 Cb 0 Y 0 Cr 0 Y 1 Cb 2 Y 2 P8-P15 BLANK (INPUT) PIXEL 0 PIXEL 1 PIXEL 2 OL0-OL2, M1, M0 Y N PIXEL N BLANK (OUTPUT) FIGURE 3. PIXEL AND OVERLAY INPUT TIMING 6-BIT YCBCR WITHOUT 2X UPSCALING Y 0Y 1Y 2Y 3Y 4Y 5 CLK P8-P15 BLANK (INPUT) Cb 0 Cr 0 Cb 2 Cr 2 Cb 4 Cr 4 P0-P7 PIXEL 0 PIXEL 1 PIXEL 2 PIXEL 3 PIXEL 4 PIXEL 5 OL0-OL2, M1, M0 CLK2 Y N Cr N-1 PIXEL N BLANK (OUTPUT) HMP8156 |
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Similar Description - HMP8156 |
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