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HMP8156EVAL1 Datasheet(PDF) 6 Page - Intersil Corporation |
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HMP8156EVAL1 Datasheet(HTML) 6 Page - Intersil Corporation |
6 / 33 page 6 8-Bit YCbCr Format without 2X Upscaling When 8-bit YCbCr format is selected and 2X upscaling is not enabled, the data is latched on each rising edge of CLK2. The pixel data must be [Cb Y Cr Y’ Cb Y Cr Y’. . . ], with the first active data each scan line being Cb data. Overlay data is latched when the Y input data is latched. The pixel and overlay input timing is shown in Figure 1. As inputs, BLANK, HSYNC, and VSYNC are latched on each rising edge of CLK2. As outputs, BLANK, HSYNC, and VSYNC are output following the rising edge of CLK2. If the CLK pin is configured as an input, it is ignored. If configured as an output, it is one-half the CLK2 frequency 8-Bit YCbCr Format with 2X Upscaling When 8-bit YCbCr format is selected, the data is latched on the rising edge of CLK2 while CLK is low. The pixel data must be [Cb Y Cr Y’ Cb Y Cr Y’. . . ], with the first active data each scan line being Cb data. Overlay data is latched on the rising edge of CLK2 that latches Y pixel input data. The pixel and overlay input timing is shown in Figure 2. As inputs, BLANK, HSYNC, and VSYNC are latched on the rising edge of CLK2 while CLK is low. As outputs, HSYNC, VSYNC, and BLANK are output following the rising edge of CLK2 while CLK is high. In this mode of operation, CLK is one-half the CLK2 frequency. TABLE 5. PIXEL INPUT AND CONTROL SIGNAL I/O TIMING INPUT FORMAT INPUT PORT SAMPLING VIDEO TIMING CONTROL (NOTE) CLK FREQUENCY PIXEL DATA OVERLAY DATA INPUT SAMPLE OUTPUT ON INPUT OUTPUT 8-Bit YCbCr Off Every rising edge of CLK2 Same edge that latches Y Every rising edge of CLK2 Any rising edge of CLK2 Ignored One-half CLK2 On Rising edge of CLK2 when CLK is low. Same edge that latches Y data Rising edge of CLK2 when CLK is low. Rising edge of CLK2 when CLK is high. One-half CLK2 16-Bit YCbCr, 16-Bit RGB, or 24-Bit RGB Off Rising edge of CLK2 when CLK is low Rising edge of CLK2 when CLK is high. One-half CLK2 On 2nd rising edge of CLK2 when CLK is low Either rising CLK2 edge when CLK is high One-fourth CLK2 BT.656 Off Every rising edge of CLK2 Same edge that latches Y Not Allowed Any rising edge of CLK2 Ignored One-half CLK2 On Not Available NOTE: Video timing control signals include HSYNC, VSYNC, BLANK and FIELD. The sync and blanking I/O directions are independent; FIELD is always an output. FIGURE 1. PIXEL AND OVERLAY INPUT TIMING - 8-BIT YCBCR WITHOUT 2X UPSCALING Cb 0 Y 0 Cr 0 Y 1 Cb 2 Y 2 CLK2 P8-P15 BLANK (INPUT) PIXEL 0 PIXEL 1 PIXEL 2 OL0-OL2, M1, M0 Y N PIXEL N BLANK (OUTPUT) HMP8156 |
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