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HMP8173 Datasheet(PDF) 4 Page - Intersil Corporation |
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HMP8173 Datasheet(HTML) 4 Page - Intersil Corporation |
4 / 33 page 4 8-Bit YCbCr Format When 8-bit YCbCr format is selected, the data is latched on each rising edge of CLK2. The pixel data must be [Cb Y Cr Y’ Cb Y Cr Y’ . . . ], with the first active data each scan line being Cb data. The pixel input timing is shown in Figure 1. As inputs, BLANK, HSYNC, and VSYNC are latched on each rising edge of CLK2. As outputs, BLANK, HSYNC, and VSYNC are output following the rising edge of CLK2. If the CLK pin is configured as an input, it is ignored. If configured as an output, it is one-half the CLK2 frequency. 16-Bit YCbCr Format When 16-bit YCbCr format is selected, the pixel data is latched on the rising edge of CLK2 while CLK is low. The pixel input timing is shown in Figure 2. As inputs, BLANK, HSYNC, and VSYNC are latched on the rising edge of CLK2 while CLK is low. As outputs, HSYNC, VSYNC, and BLANK are output following the rising edge of CLK2 while CLK is high. In these modes of operation, CLK is one-half the CLK2 frequency. 8-Bit BT.656 Format When BT.656 format is selected, data is latched on each rising edge of CLK2. The pixel input timing is shown in Figure 3. The figure shows the EAV code at the end of the line. The format of the SAV and EAV codes are shown in Table 3. The BT.656 input may also include ancillary data to load the VBI or RTCI data registers. The HMP817x will use the ancillary data when enabled in the VBI data input and Timing I/O registers. The ancillary data formats and the enable registers are described later in this data sheet. As inputs, the BLANK, HSYNC, and VSYNC pins are ignored since all timing is derived from the EAV and SAV sequences within the data stream. As outputs, BLANK, HSYNC and VSYNC are output following the rising edge of CLK2. If the CLK pin is configured as an input, it is ignored. If configured as an output, it is one-half the CLK2 frequency. FIGURE 1. PIXEL INPUT TIMING - 8-BIT YCBCR FIGURE 2. PIXEL INPUT TIMING - 16-BIT YCBCR Cb 0 Y 0 Cr 0 Y 1 Cb 2 Y 2 CLK2 P8-P15 BLANK (INPUT) Y N BLANK (OUTPUT) Y 0Y 1Y 2Y 3Y 4Y 5 CLK P8-P15 BLANK (INPUT) Cb 0 Cr 0 Cb 2 Cr 2 Cb 4 Cr 4 P0-P7 CLK2 Y N Cr N-1 BLANK (OUTPUT) HMP8170, HMP8171, HMP8172, HMP8173 |
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