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5962D9567002VCA Datasheet(PDF) 2 Page - Intersil Corporation |
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5962D9567002VCA Datasheet(HTML) 2 Page - Intersil Corporation |
2 / 6 page 2 Test Circuit NOTE: Includes stray capacitances. Timing Waveforms FIGURE 1. SIMPLIFIED TEST CIRCUIT FIGURE 2. SLEW RATE WAVEFORM FIGURE 3. TRANSIENT RESPONSE WAVEFORM NOTE: Measured on both positive and negative transitions. Capacitance at Compensation pin should be minimized. S8 S5A 2 1 100 100 +VCC S5B 2 1 + OPEN 1 2K -VEE OPEN S9 1 2 75pF (NOTE) ACOUT 1 V2 EOUT 50K 1 10K S1 + -1 50K V1 S2 S6 1 2 DUT S3B 2 OPEN 1 1 0.1 500K BUFFER FOR LOOP STABILITY, USE MIN VALUE CAPACITOR TO PREVENT OSCILLATION OPEN 2 OPEN 2 10K S3A 1 0.1 400 1.6K 1 OPEN 2 ALL RESISTORS = ±1% (Ω) ALL CAPACITORS = ±10% (µF) -1/10 2 - + - 2 x - VAC VIN VOUT 1.6K 75pF 400 + - +1.0V INPUT -4V +2.5V OUTPUT -2.5V SLEW RATE = ∆V/∆T ∆T -1.0V +4V ∆V +40mV INPUT 0V OVERSHOOT 90% OUTPUT 10% RISE TIME -40mV 0V 0V +160mV HS-2700RH |
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