Electronic Components Datasheet Search |
|
HSP43891VC-20 Datasheet(PDF) 5 Page - Intersil Corporation |
|
HSP43891VC-20 Datasheet(HTML) 5 Page - Intersil Corporation |
5 / 18 page 5 Functional Description The Digital Filter Processor (DF) is composed of eight filter cells cascaded together and an output stage for combining or selecting filter cell outputs (See Block Diagram). Each filter cell contains a multiplier-accumulator and several registers (Figure 1). Each 9-bit coefficient is multiplied by a 9-bit data sample, with the result added to the 26-bit accumulator contents. The coefficient output of each cell is cascaded to the coefficient input of the next cell to its right. DF Filter Cell A 9-bit coefficient (CIN0-8) enters each cell through the C register on the left and exits the cell on the right as signals COUT0-8. With no decimation, the coefficient moves directly from the C register to the output, and is valid on the clock following its entrance. When decimation is selected the coefficient exit is delayed by 1, 2 or 3 clocks by passing through one or more decimation registers (D1, D2 or D3). The combination of D registers through which the coefficient passes is determined by the state of DCM0 and DCM1. The output signals (COUT0-8) are connected to the CIN0-8 inputs of the next cell to its right. The COENB input signal enables the COUT0-8 outputs of the right most cell to the COUT0-8 pins of the device. The C and D registers are enabled for loading by CIENB. Loading is synchronous with CLK when CIENB is low. Note that CIENB is latched internally. It enables the register for loading after the next CLK following the onset of CIENB low. Actual loading occurs on the second CLK following the onset of CIENB low. Therefore CIENB must be low during the clock cycle immediately preceding presentation of the coefficient on the CIN0-8 inputs. In most basic FIR operations, CIENB will be low throughout the process, so this latching and delay sequence is only important during the initialization phase. When CIENB is high, the coefficients are frozen. The C and D registers are cleared synchronously under control of RESET, which is latched and delayed exactly like CIENB. The output of the C register (C0-8) is one input to 9 x 9 multiplier. The other input to the 9 x 9 multiplier comes from the output of the X register. This register is loaded with a data sample from the device input signals DIN0-8 discussed above. The X register is enabled for loading by DIENB. Loading is synchronous with CLK when DIENB is low. Note that DIENB is latched internally. It enables the register for loading after the next CLK following the onset of DIENB low. Actual loading occurs on the second CLK following the onset of DIENB low; therefore, DIENB must be low during the clock SUM0-25 F9, G9-G11, H10, H11, J2, J5-J7, J10, K2, K5, K7-K11, L2-L6, L8, L10, L11 O These 26 three-state outputs are used to output the results of the internal filter cell computations. Indi- vidual filter cell results or the result of the shift and add output stage can be output. If an individual filter cell result is to be output, the ADR0-2 signals select the filter cell result. The SHADD signal determines whether the selected filter cell result or the output stage adder result is output. The signals SENBH and SENBL enable the most significant and least significant bits of the SUM0-25 result respectively. Both SENBH and SENBL may be enabled simultaneously if the system has a 26-bit or larger bus. However individual enables are provided to facilitate use with a 16-bit bus. SENBH K1 I A low on this input enables result bits SUM16-25. A high on this input places these bits in their high impedance state. SENBL E11 I A low on this input enables result bits SUM0-15. A high on this input places these bits in their high im- pedance state. ADR0-2 G1, H1, H2 I These three inputs select the one cell whose accumulator will be read through the output bus (SUM0- 25) or added to the output stage accumulator. They also determine which accumulator will be cleared when ERASE is low. These inputs are latched in the DF and delayed by one clock internal to the device. If ADR0-2 remains at the same address for more than one clock, the output at SUM0-25 will not change to reflect any subsequent accumulator updates in the addressed cell. Only the result available during the first clock, when ADR0-2 selects the cell, will be output. This does not hinder normal operation since the ADR0-2 lines are changed sequentially. This feature facilitates the interface with slow memories where the output is required to be fixed for more than one clock. SHADD F3 I The SHADD input controls the activation of the shift and add operation in the output stage. This signal is latched on chip and delayed by one clock internal to the device. Detailed explanation is given in the DF Output Stage section. RESET A4 I A low on this input synchronously clears all the internal registers, except the cell accumulators It can be used with ERASE to also clear all the accumulators simultaneously. This signal is latched in the DF and delayed by one clock internal to the device. ERASE B4 I A low on this input synchronously clears the cell accumulator selected by the ADR0-2 signals. If RESET is also low simultaneously, all cell accumulators are cleared. Pin Description (Continued) SYMBOL PIN NUMBER TYPE NAME AND FUNCTION HSP43891 |
Similar Part No. - HSP43891VC-20 |
|
Similar Description - HSP43891VC-20 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |