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HSP43891VC-30 Datasheet(PDF) 10 Page - Intersil Corporation |
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HSP43891VC-30 Datasheet(HTML) 10 Page - Intersil Corporation |
10 / 18 page 10 Detailed operation of the DF to perform a basic 8-tap, 9-bit coefficient, 9-bit data, 30MHz FIR filter is best understood by observing the schematic (Figure 3) and timing diagram (Figure 4). The internal pipeline length of the DF is four (4) clock cycles, corresponding to the register levels CREG (or XREG), MREG0, MREG1, and TREG (Figures 1 and 2). Therefore, the delay from presentation of data and coefficients at the DIN0-8 and CIN0-8 inputs to a sum appearing at the SUM0-25 output is: k + Td, where k = filter length and Td = 4, the internal pipeline delay of the DF. After the pipeline has filled, a new output sample is available every clock. The delay to last sample output from last sample input is Td. The output sums, YN, shown in the timing diagram are derived from the sum-of-products equation. Y N = 7 Σ K0 = C K XNK – C7 C6 C5 C4 C3 C2 C1 C0 C7 C6 C5 C4 C3 C2 C1 C0 C7 C6 C5 0123456789 10 11 12 13 14 15 16 17 18 19 20 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 012345670 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 CLK RESET ERASE DIN0-8 DIENB CIN0-8 CIENB ADR0-2 SUM0-25 SHADD SENBL SENBH DCM0-1 0 FIGURE 4. HSP43891 30MHz, 8-TAP FIR FILTER TIMING +5V ADR1 ADR0 ADR2 VCC SHADD SENBH SENBL DIN0-8 DIENB CLK CIN0-8 CIENB DCM1 DCM0 RESET ERASE VSS COENB COUT0-8 SUM0-25 26 SUM OUT 9 NC HSP43891 9 (YN) +5V 26 9 9 9 30MHz CLOCK Q Q C D SAMPLE DATA IN (XN) 9x16 COEFF RAM/ROM A0 A1 A2 A3 D0-D8 CLK Y0 Y1 Y2 Y3 RESET 4-BIT CTR SYSTEM RESET ADR1 ADR0 ADR2 VCC SHADD SENBH SENBL DIN0-8 DIENB CLK CIN0-8 CIENB DCM1 DCM0 RESET ERASE VSS COENB COUT0-8 SUM0-25 HSP43891 DF1 DF0 FIGURE 5. HSP43891 30MHz, 16-TAP FIR FILTER CASCADE APPLICATION SCHEMATIC HSP43891 |
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