10

Detailed operation of the DF to perform a basic 8-tap, 9-bit

coefficient, 9-bit data, 30MHz FIR filter is best understood by

observing the schematic (Figure 3) and timing diagram

(Figure 4). The internal pipeline length of the DF is four (4)

clock cycles, corresponding to the register levels CREG (or

XREG), MREG0, MREG1, and TREG (Figures 1 and 2).

Therefore, the delay from presentation of data and

coefficients at the DIN0-8 and CIN0-8 inputs to a sum

appearing at the SUM0-25 output is: k + Td, where k = filter

length and Td = 4, the internal pipeline delay of the DF. After

the pipeline has filled, a new output sample is available

every clock. The delay to last sample output from last

timing diagram are derived from the sum-of-products

equation.

Y

7

Σ

K0

=

C

–

0123456789

10

11

12

13

14

15

16

17

18

19

20

012345670

CLK

RESET

ERASE

DIN0-8

DIENB

CIN0-8

CIENB

ADR0-2

SUM0-25

SHADD

SENBL

SENBH

DCM0-1

0

FIGURE 4. HSP43891 30MHz, 8-TAP FIR FILTER TIMING

+5V

ADR1

ADR0

ADR2

SHADD

SENBH

SENBL

DIN0-8

DIENB

CLK

CIN0-8

CIENB

DCM1

DCM0

RESET

ERASE

COENB

COUT0-8

SUM0-25

26

SUM

OUT

9

NC

HSP43891

9

+5V

26

9

9

9

30MHz

CLOCK

Q

Q

C

D

SAMPLE

9x16 COEFF

RAM/ROM

D0-D8

CLK

RESET

4-BIT

CTR

SYSTEM

RESET

ADR1

ADR0

ADR2

SHADD

SENBH

SENBL

DIN0-8

DIENB

CLK

CIN0-8

CIENB

DCM1

DCM0

RESET

ERASE

COENB

COUT0-8

SUM0-25

HSP43891

DF1

DF0

FIGURE 5. HSP43891 30MHz, 16-TAP FIR FILTER CASCADE APPLICATION SCHEMATIC

HSP43891