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HSP43891GC-20 Datasheet(PDF) 8 Page - Intersil Corporation |
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HSP43891GC-20 Datasheet(HTML) 8 Page - Intersil Corporation |
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8 / 18 page  8 The 26 least significant bits (LSBs) from either a cell accumulator or the output buffer are output on the SUM0-25 bus. The output mux determines whether the cell accumulator selected by ADR0-2 or the output buffer is output to the bus. This mux is controlled by the SHADD input signal. Control is based on the state of the SHADD during two successive clocks; in other words, the output mux selection contains memory. If SHADD is low during a clock cycle and was low during the previous clock, the output mux selects the contents of the filter cell accumulator addressed by ADR0-2. Otherwise the output mux selects the contents of the output buffer. If the ADR0-2 lines remain at the same address for more than one clock, the output at SUM0-25 will not change to reflect any subsequent accumulator updates in the addressed cell. Only the result available during the first clock when ADR0-2 selects the cell will be output. This does not hinder normal FIR operation since the ADR0-2 lines are changed sequentially. This feature facilitates the interface with slow memories where the output is required to be fixed for more than one clock. The SUM0-25 output bus is controlled by the SENBH and SENBL signals. A low on SENBL enables bits SUM0-15. A low on SENBH enables bits SUM16-25. Thus, all 26 bits can be output simultaneously if the external system has a 26-bit or larger bus. If the external system bus is only 16 bits, the bits can be enabled in two groups of 16 and 10 bits (sign extended). DF Arithmetic Both data samples and coefficients can be represented as either 8-bit unsigned or 9-bit two’s complement numbers. The 9x9 bit multiplier in each cell expects 9-bit two’s complement operands. The binary format of 8-bit two’s complement is shown below. Note that if the most significant or sign bit is held at logical zero, the 9-bit two’s complement multiplier can multiply 8-bit unsigned operands. Only the upper (positive) half of the two’s complement binary range is used. The multiplier output is 18 bits and the accumulator is 26 bits. The accumulator width determines the maximum possible number of terms in the sum of products without overflow. The maximum number of terms depends also on the number system and the distribution of the coefficient and data values. Then maximum numbers of terms in the sum products are: For practical FIR filters, the coefficients are never all near maximum value, so even larger vectors are possible in practice. Basic FIR Operation A simple, 30MHz 8-tap filter example serves to illustrate more clearly the operation of the DF. The sequence table (Table 1) shows the results of the multiply accumulate in each cell after each clock. The coefficient sequence, CN, enters the DF on the left and moves from left to right through the cells. The data sample sequence, XN, enters the DF from the top, with each cell receiving the same sample simultaneously. Each cell accumulates the sum of products for one output point. Eight sums of products are calculated simultaneously, but staggered in time so that a new output is available every system clock. 26 0-18 OUTPUT RESET.D SIGN EXT CELL RESULT MUX 3 CELL RESULTS 26 0 26 1 26 6 26 7 ADR0.D - ADR2.D 18 8 18-25 18 (LSBs) 0-17 26 + BUFFER CLK 26 26 26 OUTPUT MUX 10 26 3-STATE BUFFER 26 SUM0-25 18 MUX ZERO 01 0’s 0-17 8-25 18 MSBs SHIFTED 8 BITS TO RIGHT 2 SENBL SENBH CLK CLR D Q RESET.D CLK CLR D Q RESET.D SHADD SHADD.D FIGURE 2. HSP43891 DFP OUTPUT STAGE NUMBER SYSTEM MAXIMUM # OF TERMS 8-BIT 9-BIT Two Unsigned Vectors 1032 N/A Two Two’s Complement Vectors • Two Positive Vectors 2080 1032 • Negative Vectors 2047 1024 • One Positive and One Negative Vector 2064 1028 One Unsigned 8-Bit Vector and One Two’s Complement Vector • Positive Two’s Complement Vector 1036 1032 • Negative Two’s Complement Vector 1028 1028 HSP43891 |
Similar Part No. - HSP43891GC-20 |
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