11

FCT0-2 Hold from LD

0-0-

ns

START Setup to CLK

12-13-

ns

START Hold from CLK

0-0-

ns

PIN0-9 Setup Time

12-13-

ns

PIN0-9 Hold Time

0-0-

ns

LD Pulse Width

10-12-

ns

Note 7

-ns

WR Low

12-15-

ns

WR High

12-15-

ns

Address Setup

13-15-

ns

Address Hold

1-1-

ns

DIO Setup to WR

12-15-

ns

DIO Hold from WR

1-1-

ns

RD Low

35-43-

ns

RD High

15-17-

ns

RD Low to DIO Valid

-35-43

ns

Read/Write Cycle Time

55-65-

ns

DIO Valid after RD High

Note 8

-

0

-

0

ns

Output Enable Time

Note 9

-

18

-

19

ns

Output Disable Time

Note 8

-

18

-

19

ns

Output Rise Time

From 0.8V to 2.0V, Note 8

-

6

-

6

ns

Output Fall Time

From 2.0V to 0.8V, Note 8

-

6

-

6

ns

NOTES:

6. AC Testing is performed as follows: Input levels (CLK) 0.0V and 4.0V; input levels (all other inputs) 0V and 3.0V. Timing reference levels (CLK)

7. There must be at least one rising edge of CLK between the rising edge of LD and the falling edge of START.

8. Characterized upon initial design and after major changes to design and/or process.

9. Transition is measured at

AC Electrical Specifications

PARAMETER

SYMBOL

NOTES

-40 (40 MHz)

-33 (33 MHz)

UNITS

MIN

MAX

MIN

MAX

Test Load Circuit

EQUIVALENT CIRCUIT

IOH

1.5V

IOL

DUT

±

HSP48410