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HSP48410GC-40 Datasheet(PDF) 11 Page - Intersil Corporation |
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HSP48410GC-40 Datasheet(HTML) 11 Page - Intersil Corporation |
11 / 12 page 11 FCT0-2 Hold from LD tFH 0-0- ns START Setup to CLK tSS 12-13- ns START Hold from CLK tSH 0-0- ns PIN0-9 Setup Time tPS 12-13- ns PIN0-9 Hold Time tPH 0-0- ns LD Pulse Width tLL 10-12- ns LD Setup to STARTtLS Note 7 TCP TCP -ns WR Low tWL 12-15- ns WR High tWH 12-15- ns Address Setup tAS 13-15- ns Address Hold tAH 1-1- ns DIO Setup to WR tWS 12-15- ns DIO Hold from WR tWH 1-1- ns RD Low tRL 35-43- ns RD High tRH 15-17- ns RD Low to DIO Valid tRD -35-43 ns Read/Write Cycle Time tCY 55-65- ns DIO Valid after RD High tOH Note 8 - 0 - 0 ns Output Enable Time tOE Note 9 - 18 - 19 ns Output Disable Time tOD Note 8 - 18 - 19 ns Output Rise Time tR From 0.8V to 2.0V, Note 8 - 6 - 6 ns Output Fall Time tF From 2.0V to 0.8V, Note 8 - 6 - 6 ns NOTES: 6. AC Testing is performed as follows: Input levels (CLK) 0.0V and 4.0V; input levels (all other inputs) 0V and 3.0V. Timing reference levels (CLK) = 2.0V, (all others) = 1.5V. Output load circuit with CL = 40pF. Output transition measured at VOH ≥ 1.5V and VOL ≤ 1.5V. 7. There must be at least one rising edge of CLK between the rising edge of LD and the falling edge of START. 8. Characterized upon initial design and after major changes to design and/or process. 9. Transition is measured at ±200mV from steady state voltage with loading as specified in test load circuit with CL = 40pF. AC Electrical Specifications VCC = 5V ± 5%, TA = 0 oC to 70oC (Note 6) (Continued) PARAMETER SYMBOL NOTES -40 (40 MHz) -33 (33 MHz) UNITS MIN MAX MIN MAX Test Load Circuit EQUIVALENT CIRCUIT CL† IOH 1.5V IOL DUT S1 SWITCH S1 OPEN FOR ICCSB AND ICCOP ± †INCLUDES STRAY AND JIG CAPACITANCE HSP48410 |
Similar Part No. - HSP48410GC-40 |
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Similar Description - HSP48410GC-40 |
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