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HSP50216KI Datasheet(PDF) 8 Page - Intersil Corporation |
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HSP50216KI Datasheet(HTML) 8 Page - Intersil Corporation |
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8 / 53 page  8 Level Detector An input level detector is provided to monitor the signal level on any of the input busses. Which input bus, the input format, and the level detection type are programmable (see Microprocessor Interface Section Tables 37, 38 and 39, GWA’s F804h, F805h and F806h). The supported monitoring modes are: integrated magnitude (like the HSP50214 w/o the threshold), leaky integration (Yn =Xn xA+Yn-1 x (1-A)), and peak detection. The measurement interval can be programmed from 2 to 65537 samples (or continuous for the leaky integrator and peak detect cases). The output is 32 bits and is read via the µP interface. NCO/Mixer After the input select/format section, the samples are multiplied by quadrature sine wave samples from the carrier NCO. The NCO has a 32-bit frequency control, providing sub-hertz resolution at the maximum clock rate. The quadrature sinusoids have exceptional purity. The purity of the NCO should not be the determining factor for the receiver dynamic range performance. The phase quantization to the sine/cosine generator is 24 bits and the amplitude quantization is 19 bits. The carrier NCO center frequency is loaded via the µP bus. The center frequency control is double buffered - the input is loaded into a center frequency holding register via the µP interface. The data is then transferred from the holding register to the active register by a write to a address IWA *006h or by a SYNCI signal, if loading via SYNCI is enabled. To synchronize multiple channels, the carrier NCO phase accumulator feedback can be zeroed on loading to restart all of the NCOs at the same phase. A serial offset frequency input is also available for each channel through the D(15:0) parallel data input bus (if that bus is not needed for data input). This is legacy support for HSP50210 type tracking signals. After the mixers, a PN signal can be added to the data. This feature is provided for test and to digitally reduce the input sensitivity and adjust the receiver range (sensitivity). The effect is the same as increasing the noise figure of the receiver, reducing its sensitivity and overall dynamic range. The one bit PN data is scaled by a 16-bit programmable scale factor. The overall range for the PN is 0 to 1/8 full scale. A gain of 0 disables the PN input. The bit weighting for the gain is: SIGNAL (2^-): The minimum, non-zero, PN value is 1/(218) of full scale (-108dBFS) on each axis (-105dBFS total). For an input noise level of -75dBFS, this allows the SNR to be decreased in steps of 1/8dB or less. The I and Q PN codes are offset in time to decorrelate them. The PN code is selected and enabled in the test control register (F800h). The PN is added to the signal after the mix as: so the maximum level is -12dBFS and the minimum, non- zero level is -108dBFS. The PN code can be 215-1, 223-1 or 215-1 * 223-1. CIC Filter Next, the signal is filtered by a cascaded integrator/comb (CIC) filter. A CIC filter is an efficient architecture for decimation filtering. The power or magnitude squared frequency response of the CIC filter is given by: where M = Number of delays (1 for the HSP50216) N = Number of stages and R = Decimation factor. The CIC filter order is programmable from 0 to 5. The minimum decimation is 4. If the order is set to 0, there must be at least 4 clocks between samples or the decimation counter must be set to 4 to chose every 4th sample. The integrator/comb bit widths are: 69, 62, 53, 44, 34, 32, 32, 32, 32, 32. The integrators are sized for decimation factors up to 512 with 5 stages. The maximum decimation varies with the number of stages, but the maximum is 65536, limited by the decimation counter. A CIC filter has a gain of RN, where R is the decimation factor and N is the number of stages. For a 5 stage CIC, the gain is R5. The number of input bits is 24. The decimation factors that a CIC can handle depends on the sizes of the integrators. The integrators are sized to prevent more than one rollover per decimation period. In the HSP50216, the integrators are slightly oversized to reduce the quantization noise at each stage. Because the CIC filter gain can vary greatly with decimation, a barrel shifter is provided ahead of the CIC to add gain to the input signal. The shift factor is adjusted to keep the total barrel shifter and CIC filter between 0.5 and 1.0. The shift 0 1 2345678910 11 12 13 14 15 16 17 18 19 20 PN (2^): S S SXXXXXXXX X X XXXXXX GAIN REG (2^): X X XXXXXXXXX X X X X X (A POSITIVE 16-BIT VALUE IS LOADED, S = SIGN) Bit Weights 0. 1234567890123456789 Input Bits X XXXXXXXXXXXXXXXXXXX PN Value ± 0 0 0 PPPPPPPPPPPPPPPP Pf () πMf () sin πf R ----- sin ------------------------ 2N = HSP50216 |
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